aboutsummaryrefslogtreecommitdiffstats
path: root/host/lib/usrp/usrp_e100/clock_ctrl.cpp
diff options
context:
space:
mode:
authorJosh Blum <josh@joshknows.com>2011-06-06 10:21:45 +0100
committerJosh Blum <josh@joshknows.com>2011-06-06 10:21:45 +0100
commit8da2d8426e2a668b9fde31773a9e313a4ce1c2bb (patch)
tree4f047a32a431d24928992425c3f2d08bc06d001e /host/lib/usrp/usrp_e100/clock_ctrl.cpp
parentf239b8517b238923aacc161664857a7d7b830ab0 (diff)
downloaduhd-8da2d8426e2a668b9fde31773a9e313a4ce1c2bb.tar.gz
uhd-8da2d8426e2a668b9fde31773a9e313a4ce1c2bb.tar.bz2
uhd-8da2d8426e2a668b9fde31773a9e313a4ce1c2bb.zip
usrp-e100: bring up the clock as the first thing
We init the clock as the app wants it as the first thing we do. This greatly simplifies logic, no need to conditionally init. Clock config: perform soft reset, and removed ignore sync work Added open/close to iface so we can open and close w/o re-making. Other misc tweaks involving prints, etc...
Diffstat (limited to 'host/lib/usrp/usrp_e100/clock_ctrl.cpp')
-rw-r--r--host/lib/usrp/usrp_e100/clock_ctrl.cpp21
1 files changed, 7 insertions, 14 deletions
diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp
index f1b29840a..742959ae3 100644
--- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp
+++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp
@@ -172,6 +172,12 @@ public:
_chan_rate = 0.0;
_out_rate = 0.0;
+ //perform soft-reset
+ _ad9522_regs.soft_reset = 1;
+ this->send_reg(0x000);
+ this->latch_regs();
+ _ad9522_regs.soft_reset = 0;
+
//init the clock gen registers
//Note: out0 should already be clocking the FPGA or this isnt going to work
_ad9522_regs.sdo_active = ad9522_regs_t::SDO_ACTIVE_SDO_SDIO;
@@ -437,8 +443,6 @@ private:
}
void calibrate_now(void){
- set_ignore_sync_fpga_plus_codec(false); //want vco cal to sync
-
//vco calibration routine:
_ad9522_regs.vco_calibration_now = 0;
this->send_reg(0x18);
@@ -467,20 +471,9 @@ private:
_ad9522_regs.get_read_reg(addr), 24
);
_ad9522_regs.set_reg(addr, reg);
- if (_ad9522_regs.digital_lock_detect) goto finalize;
+ if (_ad9522_regs.digital_lock_detect) return;
}
UHD_MSG(error) << "USRP-E100 clock control: lock detection timeout" << std::endl;
- finalize:
-
- set_ignore_sync_fpga_plus_codec(true); //never loose sync between these two
- }
-
- void set_ignore_sync_fpga_plus_codec(bool enb){
- _ad9522_regs.divider0_ignore_sync = (enb)?1:0; // master FPGA clock ignores sync (always on, cannot be disabled by sync pulse)
- _ad9522_regs.divider1_ignore_sync = (enb)?1:0; // codec clock ignores sync (always on, cannot be disabled by sync pulse)
- this->send_reg(0x191);
- this->send_reg(0x194);
- this->latch_regs();
}
void soft_sync(void){