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authorJosh Blum <josh@joshknows.com>2010-05-27 23:09:09 +0000
committerJosh Blum <josh@joshknows.com>2010-05-27 23:09:09 +0000
commite940d0225944a210584c386d270d09b132b5514b (patch)
tree59188c0b162c29c02ed09a59b32ab84010ecf269 /host/lib/usrp/usrp_e/usrp_e_regs.hpp
parentf113ae17863729f05b6ada815b9817cd16001211 (diff)
parent4eff47a4b66eff61feffe6498b9ecebef94dc6b9 (diff)
downloaduhd-e940d0225944a210584c386d270d09b132b5514b.tar.gz
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Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Conflicts: host/utils/CMakeLists.txt
Diffstat (limited to 'host/lib/usrp/usrp_e/usrp_e_regs.hpp')
-rw-r--r--host/lib/usrp/usrp_e/usrp_e_regs.hpp12
1 files changed, 7 insertions, 5 deletions
diff --git a/host/lib/usrp/usrp_e/usrp_e_regs.hpp b/host/lib/usrp/usrp_e/usrp_e_regs.hpp
index 7f35212f4..51a47f061 100644
--- a/host/lib/usrp/usrp_e/usrp_e_regs.hpp
+++ b/host/lib/usrp/usrp_e/usrp_e_regs.hpp
@@ -78,11 +78,13 @@
#define UE_REG_GPIO_RX_DBG UE_REG_GPIO_BASE + 12
#define UE_REG_GPIO_TX_DBG UE_REG_GPIO_BASE + 14
-// each 2-bit sel field is layed out this way
-#define GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg
-#define GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic
-#define GPIO_SEL_DEBUG_0 0 // if pin is an output, debug lines from FPGA fabric
-#define GPIO_SEL_DEBUG_1 1 // if pin is an output, debug lines from FPGA fabric
+//possible bit values for sel when dbg is 0:
+#define GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg
+#define GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic
+
+//possible bit values for sel when dbg is 1:
+#define GPIO_SEL_DEBUG_0 0 // if pin is an output, debug lines from FPGA fabric
+#define GPIO_SEL_DEBUG_1 1 // if pin is an output, debug lines from FPGA fabric
////////////////////////////////////////////////////