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| author | Josh Blum <josh@joshknows.com> | 2010-10-13 14:28:52 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-10-13 14:28:52 -0700 |
| commit | c6042a0b317a6f74d2b74b259f14431f5c8246d4 (patch) | |
| tree | 3297836dc8ebeb52f9882e01f1d4abc922d436ee /host/lib/usrp/usrp2/usrp2_regs.hpp | |
| parent | 4dfb7b8cabef3097f822ac52f346cd6021cb35da (diff) | |
| download | uhd-c6042a0b317a6f74d2b74b259f14431f5c8246d4.tar.gz uhd-c6042a0b317a6f74d2b74b259f14431f5c8246d4.tar.bz2 uhd-c6042a0b317a6f74d2b74b259f14431f5c8246d4.zip | |
usrp2: added docs on flow control ricer args and using usrp2 with a switch
implemented flow control param hints in the mboard impl
Diffstat (limited to 'host/lib/usrp/usrp2/usrp2_regs.hpp')
| -rw-r--r-- | host/lib/usrp/usrp2/usrp2_regs.hpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp index bdd5194f9..c3a4d22de 100644 --- a/host/lib/usrp/usrp2/usrp2_regs.hpp +++ b/host/lib/usrp/usrp2/usrp2_regs.hpp @@ -193,14 +193,14 @@ #define U2_REG_TX_CTRL_CLEAR_STATE _SR_ADDR(SR_TX_CTRL + 1) #define U2_REG_TX_CTRL_REPORT_SID _SR_ADDR(SR_TX_CTRL + 2) #define U2_REG_TX_CTRL_POLICY _SR_ADDR(SR_TX_CTRL + 3) -#define U2_REG_TX_CTRL_CYCLES_PER_ACK _SR_ADDR(SR_TX_CTRL + 4) -#define U2_REG_TX_CTRL_PACKETS_PER_ACK _SR_ADDR(SR_TX_CTRL + 5) +#define U2_REG_TX_CTRL_CYCLES_PER_UP _SR_ADDR(SR_TX_CTRL + 4) +#define U2_REG_TX_CTRL_PACKETS_PER_UP _SR_ADDR(SR_TX_CTRL + 5) #define U2_FLAG_TX_CTRL_POLICY_WAIT (0x1 << 0) #define U2_FLAG_TX_CTRL_POLICY_NEXT_PACKET (0x1 << 1) #define U2_FLAG_TX_CTRL_POLICY_NEXT_BURST (0x1 << 2) -//enable flag for registers: cycles and packets per ack -#define U2_FLAG_TX_CTRL_ACK_ENB (1ul << 31) +//enable flag for registers: cycles and packets per update packet +#define U2_FLAG_TX_CTRL_UP_ENB (1ul << 31) #endif /* INCLUDED_USRP2_REGS_HPP */ |