aboutsummaryrefslogtreecommitdiffstats
path: root/host/lib/usrp/n230/n230_fpga_defs.h
diff options
context:
space:
mode:
authorAshish Chaudhari <ashish@ettus.com>2016-01-06 10:03:29 -0800
committerAshish Chaudhari <ashish@ettus.com>2016-01-06 10:03:29 -0800
commit04a4d6348bff100305bb7481d652c7170b8ff62c (patch)
tree1ad2dae096d3fd3682dab8c029e4aef0b70ecd81 /host/lib/usrp/n230/n230_fpga_defs.h
parent81bbb57c06feaa05406ba86abc237a2e80841226 (diff)
downloaduhd-04a4d6348bff100305bb7481d652c7170b8ff62c.tar.gz
uhd-04a4d6348bff100305bb7481d652c7170b8ff62c.tar.bz2
uhd-04a4d6348bff100305bb7481d652c7170b8ff62c.zip
n230: Fixed GPSDO detection logic
Diffstat (limited to 'host/lib/usrp/n230/n230_fpga_defs.h')
-rw-r--r--host/lib/usrp/n230/n230_fpga_defs.h13
1 files changed, 7 insertions, 6 deletions
diff --git a/host/lib/usrp/n230/n230_fpga_defs.h b/host/lib/usrp/n230/n230_fpga_defs.h
index 7e1b008ce..3aa96643f 100644
--- a/host/lib/usrp/n230/n230_fpga_defs.h
+++ b/host/lib/usrp/n230/n230_fpga_defs.h
@@ -137,10 +137,10 @@ static const double CODEC_DEFAULT_CLK_RATE = 40e6;
static const double N230_LINK_RATE_BPS = 1e9/8;
/*******************************************************************
- * GPSDO status
+ * GPSDO
*******************************************************************/
-static const uint32_t GPSDO_ST_NONE = 0x83;
-
+static const uint32_t GPSDO_UART_BAUDRATE = 115200;
+static const uint32_t GPSDO_ST_ABSENT = 0x83;
/*******************************************************************
* Register Objects
*******************************************************************/
@@ -192,11 +192,12 @@ public:
}
};
-class core_radio_status_reg_t : public soft_reg64_ro_t {
+class core_status_reg_t : public soft_reg64_ro_t {
public:
- UHD_DEFINE_SOFT_REG_FIELD(REF_LOCKED, /*width*/ 1, /*shift*/ 0); //[0]
+ UHD_DEFINE_SOFT_REG_FIELD(REF_LOCKED, /*width*/ 1, /*shift*/ 0); //[0]
+ UHD_DEFINE_SOFT_REG_FIELD(GPSDO_STATUS, /*width*/ 8, /*shift*/ 32); //[32:39]
- core_radio_status_reg_t():
+ core_status_reg_t():
soft_reg64_ro_t(fpga::rb_addr(fpga::RB_CORE_STATUS))
{ }
};