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authorMartin Braun <martin.braun@ettus.com>2015-12-18 12:22:05 -0800
committerMartin Braun <martin.braun@ettus.com>2015-12-18 12:22:05 -0800
commitafa4232e4f1082748259b06595d20badc3afbff8 (patch)
tree668834ec0f3396e9d378327dd84f8e784327581e /host/lib/usrp/e300/e300_impl.cpp
parentfc213724d3a3734d9d9373675b7e2c1ef29b4020 (diff)
parent789784fc7e8aeb12b8d8092d6874dee49712a156 (diff)
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Merge branch 'maint'
Diffstat (limited to 'host/lib/usrp/e300/e300_impl.cpp')
-rw-r--r--host/lib/usrp/e300/e300_impl.cpp15
1 files changed, 10 insertions, 5 deletions
diff --git a/host/lib/usrp/e300/e300_impl.cpp b/host/lib/usrp/e300/e300_impl.cpp
index 3242a7fe8..fae09ba63 100644
--- a/host/lib/usrp/e300/e300_impl.cpp
+++ b/host/lib/usrp/e300/e300_impl.cpp
@@ -278,15 +278,20 @@ void get_e3x0_fpga_images(const uhd::device_addr_t &device_addr,
//extract the FPGA path for the e300
switch(e300_eeprom_manager::get_mb_type(pid)) {
- case e300_eeprom_manager::USRP_E310_MB:
+ case e300_eeprom_manager::USRP_E310_SG1_MB:
fpga_image = device_addr.cast<std::string>("fpga",
- find_image_path(E310_FPGA_FILE_NAME));
- idle_image = find_image_path(E310_FPGA_IDLE_FILE_NAME);
+ find_image_path(E310_SG1_FPGA_FILE_NAME));
+ idle_image = find_image_path(E3XX_SG1_FPGA_IDLE_FILE_NAME);
+ break;
+ case e300_eeprom_manager::USRP_E310_SG3_MB:
+ fpga_image = device_addr.cast<std::string>("fpga",
+ find_image_path(E310_SG3_FPGA_FILE_NAME));
+ idle_image = find_image_path(E3XX_SG3_FPGA_IDLE_FILE_NAME);
break;
case e300_eeprom_manager::USRP_E300_MB:
fpga_image = device_addr.cast<std::string>("fpga",
find_image_path(E300_FPGA_FILE_NAME));
- idle_image = find_image_path(E300_FPGA_IDLE_FILE_NAME);
+ idle_image = find_image_path(E3XX_SG1_FPGA_IDLE_FILE_NAME);
break;
case e300_eeprom_manager::UNKNOWN:
default:
@@ -294,7 +299,7 @@ void get_e3x0_fpga_images(const uhd::device_addr_t &device_addr,
<< std::endl;
fpga_image = device_addr.cast<std::string>("fpga",
find_image_path(E300_FPGA_FILE_NAME));
- idle_image = find_image_path(E300_FPGA_IDLE_FILE_NAME);
+ idle_image = find_image_path(E3XX_SG1_FPGA_IDLE_FILE_NAME);
break;
}
}