e300: Added minimum master clock rate restriction

- Master clock rate cannot be less than 10 MHz, which is the
  MMCM's minimum operating frequency in the FPGA's capture
  interface.

1 files changed, 11 insertions, 0 deletions

diff --git a/host/lib/usrp/e300/e300_impl.cpp b/host/lib/usrp/e300/e300_impl.cpp
index 3d92bc5c8..5ec2f5b2a 100644
--- a/host/lib/usrp/e300/e300_impl.cpp
+++ b/host/lib/usrp/e300/e300_impl.cpp
@@ -644,6 +644,17 @@ void e300_impl::_enforce_tick_rate_limits(
                     % direction
             ));
         }
+        // Minimum rate restriction due to MMCM used in capture interface to AD9361.
+        // Xilinx Artix-7 FPGA MMCM minimum input frequency is 10 MHz.
+        const double min_tick_rate = uhd::usrp::e300::MIN_TICK_RATE;
+        if (tick_rate - min_tick_rate < 0.0)
+        {
+            throw uhd::value_error(boost::str(
+                boost::format("current master clock rate (%.6f MHz) set below minimum possible master clock rate (%.6f MHz)")
+                    % (tick_rate/1e6)
+                    % (min_tick_rate/1e6)
+            ));
+        }
     }
 }