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authorJonathon Pendlum <jonathon.pendlum@ettus.com>2015-04-24 15:57:28 -0700
committerJonathon Pendlum <jonathon.pendlum@ettus.com>2015-04-24 15:57:28 -0700
commit65428849a51a9c6d74dff1f935b57d1ba904e5a6 (patch)
tree830a413ebc4b123a44727dbd00d976acafc0d35e /host/lib/usrp/e300/e300_defaults.hpp
parent64990acea741768becafb3e9dee171274f23f9d9 (diff)
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e300: Added minimum master clock rate restriction
- Master clock rate cannot be less than 10 MHz, which is the MMCM's minimum operating frequency in the FPGA's capture interface.
Diffstat (limited to 'host/lib/usrp/e300/e300_defaults.hpp')
-rw-r--r--host/lib/usrp/e300/e300_defaults.hpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/host/lib/usrp/e300/e300_defaults.hpp b/host/lib/usrp/e300/e300_defaults.hpp
index 537a0cf3e..7a8d49719 100644
--- a/host/lib/usrp/e300/e300_defaults.hpp
+++ b/host/lib/usrp/e300/e300_defaults.hpp
@@ -24,7 +24,7 @@ namespace uhd { namespace usrp { namespace e300 {
static const double DEFAULT_TICK_RATE = 32e6;
static const double MAX_TICK_RATE = 50e6;
-static const double MIN_TICK_RATE = 1e6;
+static const double MIN_TICK_RATE = 10e6;
static const double DEFAULT_TX_SAMP_RATE = 1.0e6;
static const double DEFAULT_RX_SAMP_RATE = 1.0e6;