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| author | Sugandha Gupta <sugandha.gupta@ettus.com> | 2019-03-05 11:37:13 -0800 |
|---|---|---|
| committer | michael-west <michael.west@ettus.com> | 2019-05-21 16:15:52 -0700 |
| commit | 41f732a4c8bb9df116a01958f0914708475097df (patch) | |
| tree | ed120de75199f9c4dc7781610e2aa3c8436a222b /host/lib/usrp/common/ad9361_driver/ad9361_device.h | |
| parent | 94908dc612676b3f9afc2f32812e1cc23542dcde (diff) | |
| download | uhd-41f732a4c8bb9df116a01958f0914708475097df.tar.gz uhd-41f732a4c8bb9df116a01958f0914708475097df.tar.bz2 uhd-41f732a4c8bb9df116a01958f0914708475097df.zip | |
ad9361: Fix return values for tune and set_clock_rate
This fixes a potential mismatch between the returned frequency and
clock rate and the actual value. The new function get_clock_rate is
need for async call to set_clock_rate in E3xx devices
Diffstat (limited to 'host/lib/usrp/common/ad9361_driver/ad9361_device.h')
| -rw-r--r-- | host/lib/usrp/common/ad9361_driver/ad9361_device.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_device.h b/host/lib/usrp/common/ad9361_driver/ad9361_device.h index 2a81118ce..b3256b4c4 100644 --- a/host/lib/usrp/common/ad9361_driver/ad9361_device.h +++ b/host/lib/usrp/common/ad9361_driver/ad9361_device.h @@ -161,6 +161,9 @@ public: /* Set SPI interface */ void set_io_iface(ad9361_io::sptr io_iface); + /* Get the current clock rate. */ + double get_clock_rate(); + /* This function sets the RX / TX rate between AD9361 and the FPGA, and * thus determines the interpolation / decimation required in the FPGA to * achieve the user's requested rate. |