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| author | Martin Braun <martin.braun@ettus.com> | 2015-09-30 18:23:20 -0700 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2015-10-14 13:39:09 -0700 |
| commit | 965b9a17cce1dc69cf907d2d551eae754aafcd49 (patch) | |
| tree | 7bbf77f2826e4ee290b5f633aa2102d228b05c57 /host/lib/usrp/common/ad9361_ctrl.hpp | |
| parent | c77ffb3e506a6fd80ba42d023a609a3653f02f2e (diff) | |
| download | uhd-965b9a17cce1dc69cf907d2d551eae754aafcd49.tar.gz uhd-965b9a17cce1dc69cf907d2d551eae754aafcd49.tar.bz2 uhd-965b9a17cce1dc69cf907d2d551eae754aafcd49.zip | |
b200: Updated minimum clock rate to match DCM changes
Lowest master clock rate is now 220 kHz. At low clock rates,
the convergence time for the DC offset and quadrature calibration
times is much larger, though.
Diffstat (limited to 'host/lib/usrp/common/ad9361_ctrl.hpp')
| -rw-r--r-- | host/lib/usrp/common/ad9361_ctrl.hpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/host/lib/usrp/common/ad9361_ctrl.hpp b/host/lib/usrp/common/ad9361_ctrl.hpp index 5c438ee9c..8cd75d539 100644 --- a/host/lib/usrp/common/ad9361_ctrl.hpp +++ b/host/lib/usrp/common/ad9361_ctrl.hpp @@ -89,8 +89,10 @@ public: //! get the clock rate range for the frontend static uhd::meta_range_t get_clock_rate_range(void) { - //return uhd::meta_range_t(220e3, 61.44e6); - return uhd::meta_range_t(5e6, ad9361_device_t::AD9361_MAX_CLOCK_RATE); //5 MHz DCM low end + return uhd::meta_range_t( + ad9361_device_t::AD9361_MIN_CLOCK_RATE, + ad9361_device_t::AD9361_MAX_CLOCK_RATE + ); } //! set the filter bandwidth for the frontend's analog low pass |