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| author | Martin Braun <martin.braun@ettus.com> | 2017-01-30 09:40:02 +0100 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2017-01-30 09:40:02 +0100 |
| commit | 211c590f594f83dc8b5fc724d49c1c8d7207d2f2 (patch) | |
| tree | 16b03b97da7c61930053a0b8699a36d36e9857b2 /host/docs | |
| parent | 207903d343f6cb520d86e62c2ebee2e847546f7b (diff) | |
| parent | 75e6ae59b3f4832372c08d7da390c5fdcc283067 (diff) | |
| download | uhd-211c590f594f83dc8b5fc724d49c1c8d7207d2f2.tar.gz uhd-211c590f594f83dc8b5fc724d49c1c8d7207d2f2.tar.bz2 uhd-211c590f594f83dc8b5fc724d49c1c8d7207d2f2.zip | |
Merge branch 'maint'
Diffstat (limited to 'host/docs')
| -rw-r--r-- | host/docs/usrp_e3x0.dox | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/host/docs/usrp_e3x0.dox b/host/docs/usrp_e3x0.dox index 470f6a26b..929b9f635 100644 --- a/host/docs/usrp_e3x0.dox +++ b/host/docs/usrp_e3x0.dox @@ -18,7 +18,6 @@ - FPGA Capabilities: - 2 RX DDC chains in FPGA - 2 TX DUC chain in FPGA - - Timed commands in FPGA - Timed sampling in FPGA - 16-bit fixed point sample mode (sc16) |