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authorWade Fife <wade.fife@ettus.com>2021-06-08 19:40:46 -0500
committerAaron Rossetto <aaron.rossetto@ni.com>2021-06-10 11:56:58 -0500
commit6d3765605262016a80f71e36357f749ea35cbe5a (patch)
tree7d62d6622befd4132ac1ee085effa1426f7f53e5 /fpga/usrp3/top/x400/dts
parentf706b89e6974e28ce76aadeeb06169becc86acba (diff)
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fpga: x400: Add support for X410 motherboard FPGA
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com>
Diffstat (limited to 'fpga/usrp3/top/x400/dts')
-rw-r--r--fpga/usrp3/top/x400/dts/usrp_x410_fpga_C1.dts20
-rw-r--r--fpga/usrp3/top/x400/dts/usrp_x410_fpga_CG.dts22
-rw-r--r--fpga/usrp3/top/x400/dts/usrp_x410_fpga_X1.dts21
-rw-r--r--fpga/usrp3/top/x400/dts/usrp_x410_fpga_X4.dts20
-rw-r--r--fpga/usrp3/top/x400/dts/usrp_x410_fpga_X4C.dts22
-rw-r--r--fpga/usrp3/top/x400/dts/usrp_x410_fpga_XG.dts22
-rw-r--r--fpga/usrp3/top/x400/dts/x410-100gbe-port0.dtsi41
-rw-r--r--fpga/usrp3/top/x400/dts/x410-100gbe-port1.dtsi41
-rw-r--r--fpga/usrp3/top/x400/dts/x410-10gbe-port0-x4.dtsi134
-rw-r--r--fpga/usrp3/top/x400/dts/x410-10gbe-port0.dtsi41
-rw-r--r--fpga/usrp3/top/x400/dts/x410-10gbe-port1-x4.dtsi134
-rw-r--r--fpga/usrp3/top/x400/dts/x410-10gbe-port1.dtsi41
-rw-r--r--fpga/usrp3/top/x400/dts/x410-common.dtsi28
-rw-r--r--fpga/usrp3/top/x400/dts/x410-dma.dtsi50
-rw-r--r--fpga/usrp3/top/x400/dts/x410-fpga.dtsi9
-rw-r--r--fpga/usrp3/top/x400/dts/x410-rfdc.dtsi38
16 files changed, 684 insertions, 0 deletions
diff --git a/fpga/usrp3/top/x400/dts/usrp_x410_fpga_C1.dts b/fpga/usrp3/top/x400/dts/usrp_x410_fpga_C1.dts
new file mode 100644
index 000000000..00ad4d25d
--- /dev/null
+++ b/fpga/usrp3/top/x400/dts/usrp_x410_fpga_C1.dts
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2021 Ettus Research, a National Instruments Brand
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "x410-version-info.dtsi"
+
+#include "x410-fpga.dtsi"
+
+#include "x410-common.dtsi"
+
+#include "x410-rfdc.dtsi"
+
+#include "x410-dma.dtsi"
+
+#include "x410-100gbe-port0.dtsi"
diff --git a/fpga/usrp3/top/x400/dts/usrp_x410_fpga_CG.dts b/fpga/usrp3/top/x400/dts/usrp_x410_fpga_CG.dts
new file mode 100644
index 000000000..35d9238e2
--- /dev/null
+++ b/fpga/usrp3/top/x400/dts/usrp_x410_fpga_CG.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2021 Ettus Research, a National Instruments Brand
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "x410-version-info.dtsi"
+
+#include "x410-fpga.dtsi"
+
+#include "x410-common.dtsi"
+
+#include "x410-rfdc.dtsi"
+
+#include "x410-dma.dtsi"
+
+#include "x410-100gbe-port0.dtsi"
+
+#include "x410-100gbe-port1.dtsi"
diff --git a/fpga/usrp3/top/x400/dts/usrp_x410_fpga_X1.dts b/fpga/usrp3/top/x400/dts/usrp_x410_fpga_X1.dts
new file mode 100644
index 000000000..42142cd9b
--- /dev/null
+++ b/fpga/usrp3/top/x400/dts/usrp_x410_fpga_X1.dts
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2021 Ettus Research, a National Instruments Brand
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "x410-version-info.dtsi"
+
+#include "x410-fpga.dtsi"
+
+#include "x410-common.dtsi"
+
+#include "x410-rfdc.dtsi"
+
+#include "x410-dma.dtsi"
+
+#include "x410-10gbe-port0.dtsi"
+
diff --git a/fpga/usrp3/top/x400/dts/usrp_x410_fpga_X4.dts b/fpga/usrp3/top/x400/dts/usrp_x410_fpga_X4.dts
new file mode 100644
index 000000000..8fd7e450b
--- /dev/null
+++ b/fpga/usrp3/top/x400/dts/usrp_x410_fpga_X4.dts
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2021 Ettus Research, a National Instruments Brand
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "x410-version-info.dtsi"
+
+#include "x410-fpga.dtsi"
+
+#include "x410-common.dtsi"
+
+#include "x410-rfdc.dtsi"
+
+#include "x410-dma.dtsi"
+
+#include "x410-10gbe-port0-x4.dtsi"
diff --git a/fpga/usrp3/top/x400/dts/usrp_x410_fpga_X4C.dts b/fpga/usrp3/top/x400/dts/usrp_x410_fpga_X4C.dts
new file mode 100644
index 000000000..be2c23a03
--- /dev/null
+++ b/fpga/usrp3/top/x400/dts/usrp_x410_fpga_X4C.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2021 Ettus Research, a National Instruments Brand
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "x410-version-info.dtsi"
+
+#include "x410-fpga.dtsi"
+
+#include "x410-common.dtsi"
+
+#include "x410-rfdc.dtsi"
+
+#include "x410-dma.dtsi"
+
+#include "x410-10gbe-port0-x4.dtsi"
+
+#include "x410-100gbe-port1.dtsi"
diff --git a/fpga/usrp3/top/x400/dts/usrp_x410_fpga_XG.dts b/fpga/usrp3/top/x400/dts/usrp_x410_fpga_XG.dts
new file mode 100644
index 000000000..46f7c0526
--- /dev/null
+++ b/fpga/usrp3/top/x400/dts/usrp_x410_fpga_XG.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2021 Ettus Research, a National Instruments Brand
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "x410-version-info.dtsi"
+
+#include "x410-fpga.dtsi"
+
+#include "x410-common.dtsi"
+
+#include "x410-rfdc.dtsi"
+
+#include "x410-dma.dtsi"
+
+#include "x410-10gbe-port0.dtsi"
+
+#include "x410-10gbe-port1.dtsi"
diff --git a/fpga/usrp3/top/x400/dts/x410-100gbe-port0.dtsi b/fpga/usrp3/top/x400/dts/x410-100gbe-port0.dtsi
new file mode 100644
index 000000000..7b6470dd6
--- /dev/null
+++ b/fpga/usrp3/top/x400/dts/x410-100gbe-port0.dtsi
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2021 Ettus Research, a National Instruments Brand
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ */
+
+&fpga_full {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ nixge0: ethernet@1200000000 {
+ compatible = "ni,xge-enet-3.00";
+ reg = <0x12 0x00000000 0x0 0x4000
+ 0x12 0x00008000 0x0 0x2000>;
+ reg-names = "dma", "ctrl";
+
+ interrupts = <0 108 4 0 109 4>;
+ interrupt-names = "rx", "tx";
+ interrupt-parent = <&gic>;
+
+ nvmem-cells = <&eth1_addr>;
+ nvmem-cell-names = "address";
+
+ status = "okay";
+
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ link-gpios = <&gpio 94 0>;
+ };
+ };
+
+ misc_enet_regs_0: uio@120000A000 {
+ status = "okay";
+ compatible = "usrp-uio";
+ reg = <0x12 0x0000A000 0x0 0x2000>;
+ reg-names = "misc-enet-regs0";
+ };
+};
diff --git a/fpga/usrp3/top/x400/dts/x410-100gbe-port1.dtsi b/fpga/usrp3/top/x400/dts/x410-100gbe-port1.dtsi
new file mode 100644
index 000000000..6897671b9
--- /dev/null
+++ b/fpga/usrp3/top/x400/dts/x410-100gbe-port1.dtsi
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2021 Ettus Research, a National Instruments Brand
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ */
+
+&fpga_full {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ nixge1: ethernet@1200040000 {
+ compatible = "ni,xge-enet-3.00";
+ reg = <0x12 0x00040000 0x0 0x4000
+ 0x12 0x00048000 0x0 0x2000>;
+ reg-names = "dma", "ctrl";
+
+ interrupts = <0 110 4 0 111 4>;
+ interrupt-names = "rx", "tx";
+ interrupt-parent = <&gic>;
+
+ nvmem-cells = <&eth5_addr>;
+ nvmem-cell-names = "address";
+
+ status = "okay";
+
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ link-gpios = <&gpio 98 0>;
+ };
+ };
+
+ misc_enet_regs_1: uio@120004A000 {
+ status = "okay";
+ compatible = "usrp-uio";
+ reg = <0x12 0x0004A000 0x0 0x2000>;
+ reg-names = "misc-enet-regs1";
+ };
+};
diff --git a/fpga/usrp3/top/x400/dts/x410-10gbe-port0-x4.dtsi b/fpga/usrp3/top/x400/dts/x410-10gbe-port0-x4.dtsi
new file mode 100644
index 000000000..1a3b8a487
--- /dev/null
+++ b/fpga/usrp3/top/x400/dts/x410-10gbe-port0-x4.dtsi
@@ -0,0 +1,134 @@
+/*
+ * Copyright 2021 Ettus Research, a National Instruments Brand
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ */
+
+&fpga_full {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ nixge0: ethernet@1200000000 {
+ compatible = "ni,xge-enet-3.00";
+ reg = <0x12 0x00000000 0x0 0x4000
+ 0x12 0x00008000 0x0 0x2000>;
+ reg-names = "dma", "ctrl";
+
+ interrupts = <0 108 4 0 109 4>;
+ interrupt-names = "rx", "tx";
+ interrupt-parent = <&gic>;
+
+ nvmem-cells = <&eth1_addr>;
+ nvmem-cell-names = "address";
+
+ status = "okay";
+
+ phy-mode = "xgmii";
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ link-gpios = <&gpio 94 0>;
+ };
+ };
+
+ nixge0_1: ethernet@1200010000 {
+ compatible = "ni,xge-enet-3.00";
+ reg = <0x12 0x00010000 0x0 0x4000
+ 0x12 0x00018000 0x0 0x2000>;
+ reg-names = "dma", "ctrl";
+
+ interrupts = <0 108 4 0 109 4>;
+ interrupt-names = "rx", "tx";
+ interrupt-parent = <&gic>;
+
+ nvmem-cells = <&eth2_addr>;
+ nvmem-cell-names = "address";
+
+ status = "okay";
+
+ phy-mode = "xgmii";
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ link-gpios = <&gpio 95 0>;
+ };
+ };
+
+ nixge0_2: ethernet@1200020000 {
+ compatible = "ni,xge-enet-3.00";
+ reg = <0x12 0x00020000 0x0 0x4000
+ 0x12 0x00028000 0x0 0x2000>;
+ reg-names = "dma", "ctrl";
+
+ interrupts = <0 108 4 0 109 4>;
+ interrupt-names = "rx", "tx";
+ interrupt-parent = <&gic>;
+
+ nvmem-cells = <&eth3_addr>;
+ nvmem-cell-names = "address";
+
+ status = "okay";
+
+ phy-mode = "xgmii";
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ link-gpios = <&gpio 96 0>;
+ };
+ };
+
+ nixge0_3: ethernet@1200030000 {
+ compatible = "ni,xge-enet-3.00";
+ reg = <0x12 0x00030000 0x0 0x4000
+ 0x12 0x00038000 0x0 0x2000>;
+ reg-names = "dma", "ctrl";
+
+ interrupts = <0 108 4 0 109 4>;
+ interrupt-names = "rx", "tx";
+ interrupt-parent = <&gic>;
+
+ nvmem-cells = <&eth4_addr>;
+ nvmem-cell-names = "address";
+
+ status = "okay";
+
+ phy-mode = "xgmii";
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ link-gpios = <&gpio 97 0>;
+ };
+ };
+
+ misc_enet_regs_0: uio@120000A000 {
+ status = "okay";
+ compatible = "usrp-uio";
+ reg = <0x12 0x0000A000 0x0 0x2000>;
+ reg-names = "misc-enet-regs0";
+ };
+
+ misc_enet_regs_0_1: uio@120001A000 {
+ status = "okay";
+ compatible = "usrp-uio";
+ reg = <0x12 0x0001A000 0x0 0x2000>;
+ reg-names = "misc-enet-regs0-1";
+ };
+
+ misc_enet_regs_0_2: uio@120002A000 {
+ status = "okay";
+ compatible = "usrp-uio";
+ reg = <0x12 0x0002A000 0x0 0x2000>;
+ reg-names = "misc-enet-regs0-2";
+ };
+
+ misc_enet_regs_0_3: uio@120003A000 {
+ status = "okay";
+ compatible = "usrp-uio";
+ reg = <0x12 0x0003A000 0x0 0x2000>;
+ reg-names = "misc-enet-regs0-3";
+ };
+};
diff --git a/fpga/usrp3/top/x400/dts/x410-10gbe-port0.dtsi b/fpga/usrp3/top/x400/dts/x410-10gbe-port0.dtsi
new file mode 100644
index 000000000..968c9bb98
--- /dev/null
+++ b/fpga/usrp3/top/x400/dts/x410-10gbe-port0.dtsi
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2021 Ettus Research, a National Instruments Brand
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ */
+
+&fpga_full {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ nixge0: ethernet@1200000000 {
+ compatible = "ni,xge-enet-3.00";
+ reg = <0x12 0x00000000 0x0 0x4000
+ 0x12 0x00008000 0x0 0x2000>;
+ reg-names = "dma", "ctrl";
+
+ interrupts = <0 108 4 0 109 4>;
+ interrupt-names = "rx", "tx";
+ interrupt-parent = <&gic>;
+
+ nvmem-cells = <&eth1_addr>;
+ nvmem-cell-names = "address";
+
+ status = "okay";
+
+ phy-mode = "xgmii";
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ link-gpios = <&gpio 94 0>;
+ };
+ };
+
+ misc_enet_regs_0: uio@120000A000 {
+ status = "okay";
+ compatible = "usrp-uio";
+ reg = <0x12 0x0000A000 0x0 0x2000>;
+ reg-names = "misc-enet-regs0";
+ };
+};
diff --git a/fpga/usrp3/top/x400/dts/x410-10gbe-port1-x4.dtsi b/fpga/usrp3/top/x400/dts/x410-10gbe-port1-x4.dtsi
new file mode 100644
index 000000000..5f4f5c8ed
--- /dev/null
+++ b/fpga/usrp3/top/x400/dts/x410-10gbe-port1-x4.dtsi
@@ -0,0 +1,134 @@
+/*
+ * Copyright 2021 Ettus Research, a National Instruments Brand
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ */
+
+&fpga_full {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ nixge1: ethernet@1200040000 {
+ compatible = "ni,xge-enet-3.00";
+ reg = <0x12 0x00040000 0x0 0x4000
+ 0x12 0x00048000 0x0 0x2000>;
+ reg-names = "dma", "ctrl";
+
+ interrupts = <0 110 4 0 111 4>;
+ interrupt-names = "rx", "tx";
+ interrupt-parent = <&gic>;
+
+ nvmem-cells = <&eth5_addr>;
+ nvmem-cell-names = "address";
+
+ status = "okay";
+
+ phy-mode = "xgmii";
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ link-gpios = <&gpio 98 0>;
+ };
+ };
+
+ nixge1_1: ethernet@1200050000 {
+ compatible = "ni,xge-enet-3.00";
+ reg = <0x12 0x00050000 0x0 0x4000
+ 0x12 0x00058000 0x0 0x2000>;
+ reg-names = "dma", "ctrl";
+
+ interrupts = <0 110 4 0 111 4>;
+ interrupt-names = "rx", "tx";
+ interrupt-parent = <&gic>;
+
+ nvmem-cells = <&eth6_addr>;
+ nvmem-cell-names = "address";
+
+ status = "okay";
+
+ phy-mode = "xgmii";
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ link-gpios = <&gpio 99 0>;
+ };
+ };
+
+ nixge1_2: ethernet@1200060000 {
+ compatible = "ni,xge-enet-3.00";
+ reg = <0x12 0x00060000 0x0 0x4000
+ 0x12 0x00068000 0x0 0x2000>;
+ reg-names = "dma", "ctrl";
+
+ interrupts = <0 110 4 0 111 4>;
+ interrupt-names = "rx", "tx";
+ interrupt-parent = <&gic>;
+
+ nvmem-cells = <&eth7_addr>;
+ nvmem-cell-names = "address";
+
+ status = "okay";
+
+ phy-mode = "xgmii";
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ link-gpios = <&gpio 100 0>;
+ };
+ };
+
+ nixge1_3: ethernet@1200070000 {
+ compatible = "ni,xge-enet-3.00";
+ reg = <0x12 0x00070000 0x0 0x4000
+ 0x12 0x00078000 0x0 0x2000>;
+ reg-names = "dma", "ctrl";
+
+ interrupts = <0 110 4 0 111 4>;
+ interrupt-names = "rx", "tx";
+ interrupt-parent = <&gic>;
+
+ nvmem-cells = <&eth8_addr>;
+ nvmem-cell-names = "address";
+
+ status = "okay";
+
+ phy-mode = "xgmii";
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ link-gpios = <&gpio 101 0>;
+ };
+ };
+
+ misc_enet_regs_1: uio@120004A000 {
+ status = "okay";
+ compatible = "usrp-uio";
+ reg = <0x12 0x0004A000 0x0 0x2000>;
+ reg-names = "misc-enet-regs1";
+ };
+
+ misc_enet_regs_1_1: uio@120005A000 {
+ status = "okay";
+ compatible = "usrp-uio";
+ reg = <0x12 0x0005A000 0x0 0x2000>;
+ reg-names = "misc-enet-regs1-1";
+ };
+
+ misc_enet_regs_1_2: uio@120006A000 {
+ status = "okay";
+ compatible = "usrp-uio";
+ reg = <0x12 0x0006A000 0x0 0x2000>;
+ reg-names = "misc-enet-regs1-2";
+ };
+
+ misc_enet_regs_1_3: uio@120007A000 {
+ status = "okay";
+ compatible = "usrp-uio";
+ reg = <0x12 0x0007A000 0x0 0x2000>;
+ reg-names = "misc-enet-regs1-3";
+ };
+};
diff --git a/fpga/usrp3/top/x400/dts/x410-10gbe-port1.dtsi b/fpga/usrp3/top/x400/dts/x410-10gbe-port1.dtsi
new file mode 100644
index 000000000..62a82cf3b
--- /dev/null
+++ b/fpga/usrp3/top/x400/dts/x410-10gbe-port1.dtsi
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2021 Ettus Research, a National Instruments Brand
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ */
+
+&fpga_full {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ nixge1: ethernet@1200040000 {
+ compatible = "ni,xge-enet-3.00";
+ reg = <0x12 0x00040000 0x0 0x4000
+ 0x12 0x00048000 0x0 0x2000>;
+ reg-names = "dma", "ctrl";
+
+ interrupts = <0 110 4 0 111 4>;
+ interrupt-names = "rx", "tx";
+ interrupt-parent = <&gic>;
+
+ nvmem-cells = <&eth5_addr>;
+ nvmem-cell-names = "address";
+
+ status = "okay";
+
+ phy-mode = "xgmii";
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ link-gpios = <&gpio 98 0>;
+ };
+ };
+
+ misc_enet_regs_1: uio@120004A000 {
+ status = "okay";
+ compatible = "usrp-uio";
+ reg = <0x12 0x0004A000 0x0 0x2000>;
+ reg-names = "misc-enet-regs1";
+ };
+};
diff --git a/fpga/usrp3/top/x400/dts/x410-common.dtsi b/fpga/usrp3/top/x400/dts/x410-common.dtsi
new file mode 100644
index 000000000..b42266f50
--- /dev/null
+++ b/fpga/usrp3/top/x400/dts/x410-common.dtsi
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2021 Ettus Research, a National Instruments Brand
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ */
+
+&fpga_full {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ uio@1000000000 {
+ compatible = "usrp-uio";
+ reg = <0x10 0x00000000 0x0 0x1000>;
+ reg-names = "jtag-0";
+ status = "okay";
+ };
+ uio@1000080000 {
+ compatible = "usrp-uio";
+ reg = <0x10 0x00080000 0x0 0x20000>;
+ reg-names = "ctrlport-mboard-regs";
+ status = "okay";
+ };
+ uio@10000A0000 {
+ compatible = "usrp-uio";
+ reg = <0x10 0x000A0000 0x0 0x4000>;
+ reg-names = "mboard-regs";
+ status = "okay";
+ };
+};
diff --git a/fpga/usrp3/top/x400/dts/x410-dma.dtsi b/fpga/usrp3/top/x400/dts/x410-dma.dtsi
new file mode 100644
index 000000000..d90fee699
--- /dev/null
+++ b/fpga/usrp3/top/x400/dts/x410-dma.dtsi
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2021 Ettus Research, a National Instruments Brand
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ */
+
+&fpga_full {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ misc_clk_3: misc_clk_3 {
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ compatible = "fixed-clock";
+ };
+
+ // AXI DMA engine + control
+ nixge_internal: ethernet@10000A4000 {
+ compatible = "ni,xge-enet-3.00";
+ reg = <0x10 0x000A4000 0x0 0x4000
+ 0x10 0x000A8000 0x0 0x2000>;
+ reg-names = "dma", "ctrl";
+
+ clocks = <&misc_clk_3>;
+ clock-names = "bus_clk";
+
+ interrupts = <0 104 4 0 105 4>;
+ interrupt-names = "tx", "rx";
+ interrupt-parent = <&gic>;
+
+ status = "okay";
+
+ phy-mode = "internal";
+ local-mac-address = <0x00 0x01 0x02 0x03 0x04 0x05>;
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ // Misc internal Ethernet registers
+ uio@10000AA000 {
+ compatible = "usrp-uio";
+ reg = <0x10 0x000AA000 0x0 0x2000>;
+ reg-names = "misc-enet-int-regs";
+ status = "okay";
+ };
+
+};
diff --git a/fpga/usrp3/top/x400/dts/x410-fpga.dtsi b/fpga/usrp3/top/x400/dts/x410-fpga.dtsi
new file mode 100644
index 000000000..66afb4091
--- /dev/null
+++ b/fpga/usrp3/top/x400/dts/x410-fpga.dtsi
@@ -0,0 +1,9 @@
+/*
+ * Copyright 2021 Ettus Research, a National Instruments Brand
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ */
+
+&fpga_full {
+ firmware-name = "x410.bin";
+};
diff --git a/fpga/usrp3/top/x400/dts/x410-rfdc.dtsi b/fpga/usrp3/top/x400/dts/x410-rfdc.dtsi
new file mode 100644
index 000000000..039f3afab
--- /dev/null
+++ b/fpga/usrp3/top/x400/dts/x410-rfdc.dtsi
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2021 Ettus Research, a National Instruments Brand
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ */
+
+&fpga_full {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ misc_clk_1: misc_clk_1 {
+ #clock-cells = <0>;
+ clock-frequency = <40000000>;
+ compatible = "fixed-clock";
+ };
+
+ misc_clk_2: misc_clk_2 {
+ #clock-cells = <0>;
+ clock-frequency = <184320000>;
+ compatible = "fixed-clock";
+ };
+
+ rf_data_converter: usp_rf_data_converter@1000100000 {
+ clock-names = "s_axi_aclk", "m0_axis_aclk", "m2_axis_aclk", "s0_axis_aclk", "s1_axis_aclk";
+ clocks = <&misc_clk_1>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_2>;
+ compatible = "xlnx,usp-rf-data-converter-2.1";
+ num-insts = <0x1>;
+ param-list = [ 00 00 00 00 00 10 00 10 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 0f d6 ff 39 cc 97 07 40 0a d7 a3 70 3d 0a a7 40 0a d7 a3 70 3d 0a 67 40 0a 00 00 00 02 00 00 00 01 00 00 00 00 00 00 00 9e ef a7 c6 4b 37 1a 40 04 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 10 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 01 00 00 00 00 00 00 00 0f d6 ff 39 cc 97 07 40 0a d7 a3 70 3d 0a a7 40 0a d7 a3 70 3d 0a 67 40 0a 00 00 00 02 00 00 00 01 00 00 00 00 00 00 00 9e ef a7 c6 4b 37 1a 40 04 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 10 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00 00 00 9a 99 99 99 99 99 19 40 00 00 00 00 00 00 b9 40 00 00 00 00 00 00 00 00 0a 00 00 00 02 00 00 00 01 00 00 00 00 00 00 00 9e ef a7 c6 4b 37 1a 40 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00 00 00 9a 99 99 99 99 99 19 40 00 00 00 00 00 00 b9 40 00 00 00 00 00 00 00 00 0a 00 00 00 02 00 00 00 01 00 00 00 00 00 00 00 9e ef a7 c6 4b 37 1a 40 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 01 00 00 00 00 00 00 00 0f d6 ff 39 cc 97 07 40 0a d7 a3 70 3d 0a a7 40 0a d7 a3 70 3d 0a 67 40 0a 00 00 00 02 00 00 00 01 00 00 00 00 00 00 00 fc a9 f1 d2 4d 62 10 40 02 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40 00 00 00 00 00 40 9f 40 00 00 00 00 00 00 00 00 0a 00 00 00 02 00 00 00 01 00 00 00 00 00 00 00 fc a9 f1 d2 4d 62 10 40 02 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 01 00 00 00 00 00 00 00 0f d6 ff 39 cc 97 07 40 0a d7 a3 70 3d 0a a7 40 0a d7 a3 70 3d 0a 67 40 0a 00 00 00 02 00 00 00 01 00 00 00 00 00 00 00 fc a9 f1 d2 4d 62 10 40 02 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40 00 00 00 00 00 40 9f 40 00 00 00 00 00 00 00 00 0a 00 00 00 02 00 00 00 01 00 00 00 00 00 00 00 fc a9 f1 d2 4d 62 10 40 02 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00];
+ reg = <0x00000010 0x00100000 0x0 0x40000>;
+ };
+
+ rfdc_regs: uio@1000140000 {
+ status = "okay";
+ compatible = "usrp-uio";
+ reg = <0x10 0x00140000 0x0 0x20000>;
+ reg-names = "rfdc-regs";
+ };
+};
generated by cgit v1.2.3 (git 2.46.0) at 2025-10-31 01:46:10 +0000