fpga: x400: zbx: Add support for XO3 CPLD variant.

The main changes included are:
- Variant-dependent pin-out instantiation.
- Update clocking scheme in top level file
  to include XO3 PLL
- Add ability to shift outgoing data for
  the GPIO communication interface with
  the X410 FPGA.
- Include project files required to build
  the XO3 variant of the ZBX CPLD.
- Add build flow for Lattice Diamond designs.
- Add ability to build XO3 variant of ZBX CPLD.

1 files changed, 62 insertions, 29 deletions

diff --git a/fpga/usrp3/top/x400/dboards/ctrlport_byte_deserializer.v b/fpga/usrp3/top/x400/dboards/ctrlport_byte_deserializer.v
index b8fde0025..9e7e89c77 100644
--- a/fpga/usrp3/top/x400/dboards/ctrlport_byte_deserializer.v
+++ b/fpga/usrp3/top/x400/dboards/ctrlport_byte_deserializer.v
@@ -8,12 +8,18 @@
 // Description:
 //   Slave interface of CtrlPort interface serialized as byte stream.
 //   See description in ctrlport_byte_serializer module for more details.
+//   Input and output data may be driven/registered using clocks with
+//   different phases (but same frequency), this allows the capability
+//   to facilitate meeting timing on this interface.
 //
 
 `default_nettype none
 
 module ctrlport_byte_deserializer (
+  // clock domain used to register input data
   input wire ctrlport_clk,
+  // clock domain used to drive output data
+  input wire ctrlport_clk_adjusted,
   input wire ctrlport_rst,
 
   // Request
@@ -58,17 +64,19 @@ module ctrlport_byte_deserializer (
   localparam SENDING       = 2'd3;
 
   // internal registers
-  reg                     [ 1:0] state             = INIT_RX;
-  reg [NUM_BYTES_RX_WRITE*8-1:0] request_cache     = {NUM_BYTES_RX_WRITE*8 {1'b0}};
-  reg [ NUM_BYTES_TX_READ*8-1:0] response_cache    = {NUM_BYTES_TX_READ*8 {1'b0}};
-  reg                     [ 2:0] byte_counter      = 3'b0;
-  reg                            transfer_complete = 1'b0;
-  reg                            write_transfer    = 1'b0;
+  reg                     [ 1:0] state                  = INIT_RX;
+  reg [NUM_BYTES_RX_WRITE*8-1:0] request_cache          = {NUM_BYTES_RX_WRITE*8 {1'b0}};
+  reg [ NUM_BYTES_TX_READ*8-1:0] response_cache         = {NUM_BYTES_TX_READ*8 {1'b0}};
+  reg                     [ 2:0] request_byte_counter   = 3'b0;
+  reg                     [ 2:0] response_byte_counter  = 3'b0;
+  reg                            transfer_complete      = 1'b0;
+  reg                            write_transfer         = 1'b0;
 
   // input registers to relax input timing
   reg [7:0] bytestream_data_in_reg = 8'b0;
   reg       bytestream_valid_in_reg = 1'b0;
   reg       bytestream_direction_reg = 1'b0;
+
   always @ (posedge ctrlport_clk) begin
     bytestream_data_in_reg <= bytestream_data_in;
     bytestream_valid_in_reg <= bytestream_valid_in;
@@ -79,22 +87,19 @@ module ctrlport_byte_deserializer (
   always @ (posedge ctrlport_clk) begin
     if (ctrlport_rst) begin
       state                    <= INIT_RX;
-      byte_counter             <= 3'b0;
+      request_byte_counter     <= 3'b0;
       transfer_complete        <= 1'b0;
-      bytestream_output_enable <= 1'b0;
+      response_byte_counter    <= 3'b0;
 
     end else begin
       // default assignments
       transfer_complete <= 1'b0;
-      // direction defined by master
-      bytestream_output_enable <= bytestream_direction;
-      bytestream_valid_out     <= 1'b0;
 
       case (state)
         // additional cycle for switching to make sure valid signal is driven
         // from master when being in RECEIVE state
         INIT_RX: begin
-          byte_counter <= 3'b0;
+          request_byte_counter <= 3'b0;
           if (bytestream_direction_reg == 0) begin
             state <= RECEIVE;
           end
@@ -103,17 +108,17 @@ module ctrlport_byte_deserializer (
         // wait for reception of request from master
         RECEIVE: begin
           if (bytestream_valid_in_reg) begin
-            byte_counter  <= byte_counter + 1'b1;
+            request_byte_counter  <= request_byte_counter + 1'b1;
             request_cache <= {request_cache[NUM_BYTES_RX_WRITE*8-9:0], bytestream_data_in_reg};
 
             // capture write or read
-            if (byte_counter == 0) begin
+            if (request_byte_counter == 0) begin
               write_transfer <= bytestream_data_in_reg[7];
             end
 
             // wait until request completes
-            if ((write_transfer && byte_counter == NUM_BYTES_RX_WRITE-1) ||
-               (~write_transfer && byte_counter == NUM_BYTES_RX_READ-1)) begin
+            if ((write_transfer && request_byte_counter == NUM_BYTES_RX_WRITE-1) ||
+               (~write_transfer && request_byte_counter == NUM_BYTES_RX_READ-1)) begin
               transfer_complete <= 1'b1;
               state             <= WAIT_RESPONSE;
             end
@@ -127,15 +132,10 @@ module ctrlport_byte_deserializer (
         end
 
         WAIT_RESPONSE: begin
-          byte_counter <= 3'b0;
+          request_byte_counter  <= 3'b0;
+          response_byte_counter <= 3'b0;
           if (m_ctrlport_resp_ack) begin
             state <= SENDING;
-
-            if (write_transfer) begin
-              response_cache <= {5'b0, 1'b1, m_ctrlport_resp_status, 32'b0};
-            end else begin
-              response_cache <= {m_ctrlport_resp_data, 5'b0, 1'b1, m_ctrlport_resp_status};
-            end
           end
 
           //abort by host
@@ -145,14 +145,11 @@ module ctrlport_byte_deserializer (
         end
 
         SENDING: begin
-          bytestream_valid_out <= 1'b1;
-          bytestream_data_out  <= response_cache[NUM_BYTES_TX_READ*8-8+:8];
-          response_cache       <= {response_cache[NUM_BYTES_TX_READ*8-9:0], 8'b0};
-          byte_counter         <= byte_counter + 1'b1;
+          response_byte_counter <= response_byte_counter + 1'b1;
 
           // wait until request completes
-          if ((write_transfer && byte_counter == NUM_BYTES_TX_WRITE-1) ||
-             (~write_transfer && byte_counter == NUM_BYTES_TX_READ-1)) begin
+          if ((write_transfer && response_byte_counter == NUM_BYTES_TX_WRITE-1) ||
+             (~write_transfer && response_byte_counter == NUM_BYTES_TX_READ-1)) begin
             state <= INIT_RX;
           end
 
@@ -169,6 +166,42 @@ module ctrlport_byte_deserializer (
     end
   end
 
+  // Output data control
+  always @ (posedge ctrlport_clk_adjusted) begin
+    if (ctrlport_rst) begin
+      bytestream_valid_out     <= 1'b0;
+      bytestream_output_enable <= 1'b0;
+    end else begin
+
+      bytestream_valid_out     <= 1'b0;
+      // direction defined by master
+      bytestream_output_enable <= bytestream_direction;
+
+      case (state)
+        WAIT_RESPONSE: begin
+
+          if (write_transfer) begin
+            response_cache <= {5'b0, 1'b1, m_ctrlport_resp_status, 32'b0};
+          end else begin
+            response_cache <= {m_ctrlport_resp_data, 5'b0, 1'b1, m_ctrlport_resp_status};
+          end
+        end
+
+        SENDING: begin
+
+          bytestream_valid_out <= 1'b1;
+          bytestream_data_out  <= response_cache[NUM_BYTES_TX_READ*8-8+:8];
+          response_cache       <= {response_cache[NUM_BYTES_TX_READ*8-9:0], 8'b0};
+
+        end
+
+        default: begin
+          // NOP
+        end
+      endcase
+    end
+  end
+
   //----------------------------------------------------------
   // assign request to ctrlport
   //----------------------------------------------------------