Removed copy of FPGA source files.

4 files changed, 0 insertions, 206 deletions

diff --git a/fpga/usrp3/top/python/batch-build b/fpga/usrp3/top/python/batch-build
deleted file mode 100755
index fcf9ac7f5..000000000
--- a/fpga/usrp3/top/python/batch-build
+++ /dev/null
@@ -1,45 +0,0 @@
-#!/bin/bash
-
-iterations=1
-directory="."
-targets=""
-name=""
-outdir=${PWD}
-
-for arg in "$@"; do
-   if [[ $arg == "--help" ]]; then
-      echo "Usage: batch-build [options] targets"
-      echo "Options:"
-      echo "   --runs=N [1]            Build the specified targets N times"
-      echo "   --dir=<dir> [.]         Makefile directory"
-      echo "   --name=<name> [<empty>] Name of this batch job. Used as a prefix for build output"
-      echo "   --help                  Print the message and exit"
-      echo ""
-      exit 0
-   elif [[ $arg =~ "--runs="([0-9]+) ]]; then
-      iterations=${BASH_REMATCH[1]}
-   elif [[ $arg =~ "--dir="(.+) ]]; then
-      directory=${BASH_REMATCH[1]}
-   elif [[ $arg =~ "--name="(.+) ]]; then
-      name=${BASH_REMATCH[1]}"_"
-   else
-      targets=$targets$arg" "
-   fi
-done
-
-cd $directory >/dev/null 2>&1
-if [ $? -ne 0 ]; then
-   echo "ERROR: Could not cd to $directory"
-   exit
-fi
-
-for i in $(seq 1 $iterations); do
-   make $targets
-   if [ $? -ne 0 ]; then
-      echo "ERROR: Build Failed!!! Stopping batch build."
-      exit
-   fi
-   cp -rf build ${outdir}/${name}batch-build_$(date +'%Y-%m-%d_%H-%M-%S')
-   make clean
-done
-
diff --git a/fpga/usrp3/top/python/bit_to_zynq_bin.py b/fpga/usrp3/top/python/bit_to_zynq_bin.py
deleted file mode 100755
index 0d32bf656..000000000
--- a/fpga/usrp3/top/python/bit_to_zynq_bin.py
+++ /dev/null
@@ -1,62 +0,0 @@
-#!/usr/bin/python
-import sys
-import os
-import struct
-
-def flip32(data):
-	sl = struct.Struct('<I')
-	sb = struct.Struct('>I')
-	b = buffer(data)
-	d = bytearray(len(data))
-	for offset in xrange(0, len(data), 4):
-		 sb.pack_into(d, offset, sl.unpack_from(b, offset)[0])
-	return d
-
-import argparse
-parser = argparse.ArgumentParser(description='Convert FPGA bit files to raw bin format suitable for flashing')
-parser.add_argument('-f', '--flip', dest='flip', action='store_true', default=False, help='Flip 32-bit endianess (needed for Zynq)')
-parser.add_argument("bitfile", help="Input bit file name")
-parser.add_argument("binfile", help="Output bin file name")
-args = parser.parse_args()
-
-short = struct.Struct('>H')
-ulong = struct.Struct('>I')
-
-bitfile = open(args.bitfile, 'rb')
-
-l = short.unpack(bitfile.read(2))[0]
-if l != 9:
-	raise Exception, "Missing <0009> header (0x%x), not a bit file" % l
-bitfile.read(l)
-l = short.unpack(bitfile.read(2))[0]
-d = bitfile.read(l)
-if d != 'a':
-	raise Exception, "Missing <a> header, not a bit file"
-
-l = short.unpack(bitfile.read(2))[0]
-d = bitfile.read(l)
-print "Design name:", d
-
-KEYNAMES = {'b': "Partname", 'c': "Date", 'd': "Time"}
-
-while 1:
-	k = bitfile.read(1)
-	if not k:
-		raise Exception, "unexpected EOF"
-	elif k == 'e':
-		l = ulong.unpack(bitfile.read(4))[0]
-		print "found binary data:", l
-		d = bitfile.read(l)
-		if args.flip:
-			d = flip32(d)
-		open(args.binfile, 'wb').write(d)
-		break
-	elif k in KEYNAMES:
-		l = short.unpack(bitfile.read(2))[0]
-		d = bitfile.read(l)
-		print KEYNAMES[k], d
-	else:
-		print "Unexpected key: ", k
-		l = short.unpack(bitfile.read(2))[0]
-		d = bitfile.read(l)
-
diff --git a/fpga/usrp3/top/python/check_inout.py b/fpga/usrp3/top/python/check_inout.py
deleted file mode 100755
index ff371d378..000000000
--- a/fpga/usrp3/top/python/check_inout.py
+++ /dev/null
@@ -1,62 +0,0 @@
-#!/usr/bin/env python
-#
-# Copyright 2010 Ettus Research LLC
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-#
-# Description:
-# generates a list of inputs and outputs from the top-level Verilog file and cross-references them to the .ucf.
-# outputs errors for pins that aren't found in the UCF, checks for capitalization errors and other common mistakes
-
-import sys
-import re
-
-if __name__=='__main__':
-  if len(sys.argv) == 2:
-    print "Usage: %s <top level Verilog file> <pin definition UCF>"
-    sys.exit(-1)
-
-  verilog_filename = sys.argv[1]
-  ucf_filename = sys.argv[2]
-
-  verilog_file = open(verilog_filename, 'r')
-  ucf_file = open(ucf_filename, 'r')
-
-  verilog_iolist = list()
-  ucf_iolist = list()
-
-  #read in all input, inout, and output declarations and compile a list
-  for line in verilog_file:
-    for match in re.findall(r"(?:input|inout|output) (?:reg )*(?:\[.*\] )*(\w+)", line.split("//")[0]):
-      verilog_iolist.append(match)
-
-  for line in ucf_file:
-      m = re.search(r"""NET "(\w+).*" """, line.split("#")[0])
-      if m is not None:
-        ucf_iolist.append(m.group(1))
-
-  #now find corresponding matches and error when you don't find one
-  #we search for .v defs without matching .ucf defs since the reverse isn't necessarily a problem
-  err = False
-
-  for item in verilog_iolist:
-    if item not in ucf_iolist:
-      print "Error: %s appears in the top-level Verilog file, but is not in the UCF definition file!" % item
-      err = True
-
-  if err:
-    sys.exit(-1)
-
-  print "No errors found."
-  sys.exit(0)
diff --git a/fpga/usrp3/top/python/check_timing.py b/fpga/usrp3/top/python/check_timing.py
deleted file mode 100644
index 5e32141f4..000000000
--- a/fpga/usrp3/top/python/check_timing.py
+++ /dev/null
@@ -1,37 +0,0 @@
-#!/usr/bin/env python
-#
-# Copyright 2011-2012 Ettus Research LLC
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-
-import sys
-import re
-
-def print_timing_constraint_summary(twr_file):
-    output = ""
-    keep = False
-    done = False
-    try: open(twr_file)
-    except IOError:
-        print "cannot open or find %s; no timing summary to print!"%twr_file
-        exit(-1)
-    for line in open(twr_file).readlines():
-        if 'Derived Constraint Report' in line: keep = True
-        if 'constraint' in line and 'met' in line: done = True
-        if not keep and done: keep = True
-        if keep: output += line
-        if done: break
-    print("\n\n"+output)
-
-if __name__=='__main__': map(print_timing_constraint_summary, sys.argv[1:])