Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

1 files changed, 86 insertions, 0 deletions

diff --git a/fpga/usrp3/top/n3xx/mb_clocks.xdc b/fpga/usrp3/top/n3xx/mb_clocks.xdc
new file mode 100644
index 000000000..30736155f
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/mb_clocks.xdc
@@ -0,0 +1,86 @@
+#
+# Copyright 2017 Ettus Research, A National Instruments Company
+# SPDX-License-Identifier: LGPL-3.0
+#
+# Timing analysis is performed in "/n3xx/doc/mb_timing.xlsx". See
+# the spreadsheet for more details and explanations.
+
+#*******************************************************************************
+## Motherboard Clocks
+
+# 10/20/25 MHz reference clock from rear panel connector. Constrain to the fastest
+# possible clock rate.
+set REF_CLK_PERIOD 40.00
+create_clock -name ref_clk       -period $REF_CLK_PERIOD  [get_ports FPGA_REFCLK_P]
+# 125 MHz RJ45 Ethernet clock
+create_clock -name ge_phy_clk    -period 8.000            [get_ports ENET0_CLK125]
+# 156.25 MHz oscillator to MGT bank 110
+create_clock -name xge_clk       -period 6.400            [get_ports MGT156MHZ_CLK1_P]
+# 125 MHz PLL for MG bank 109
+create_clock -name net_clk       -period 8.000            [get_ports NETCLK_P]
+
+# Virtual clocks for constraining I/O (used below)
+create_clock -name async_in_clk  -period 50.00
+create_clock -name async_out_clk -period 50.00
+
+
+
+#*******************************************************************************
+## Aliases for auto-generated clocks
+
+# Rename the PS clocks. These are originally declared in the PS7 IP block, but do not
+# have super descriptive names. We rename them here for additional clarity, and to match
+# the rest of the design.
+
+# First save off the input jitter setting for each, before we nuke the original clocks.
+set clk100_jitter       [get_property INPUT_JITTER [get_clocks clk_fpga_0]]
+set clk40_jitter        [get_property INPUT_JITTER [get_clocks clk_fpga_1]]
+set meas_clk_ref_jitter [get_property INPUT_JITTER [get_clocks clk_fpga_2]]
+set bus_clk_jitter      [get_property INPUT_JITTER [get_clocks clk_fpga_3]]
+
+# Create the new clocks based on the old ones. This generates critical warnings that
+# we are completely rewriting the old clock definition... this is OK.
+create_clock -name clk100 \
+             -period   [get_property PERIOD      [get_clocks clk_fpga_0]] \
+             [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_0]]]
+create_clock -name clk40 \
+             -period   [get_property PERIOD      [get_clocks clk_fpga_1]] \
+             [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_1]]]
+create_clock -name meas_clk_ref \
+             -period   [get_property PERIOD      [get_clocks clk_fpga_2]] \
+             [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_2]]]
+create_clock -name bus_clk \
+             -period   [get_property PERIOD      [get_clocks clk_fpga_3]] \
+             [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_3]]]
+
+# Apply the jitter setting from the original clocks.
+set_input_jitter [get_clocks clk100]       $clk100_jitter
+set_input_jitter [get_clocks clk40]        $clk40_jitter
+set_input_jitter [get_clocks meas_clk_ref] $meas_clk_ref_jitter
+set_input_jitter [get_clocks bus_clk]      $bus_clk_jitter
+
+
+# TDC Measurement Clock
+create_generated_clock -name meas_clk_fb [get_pins {n3xx_clocking_i/misc_clock_gen_i/inst/mmcm_adv_inst/CLKFBOUT}]
+create_generated_clock -name meas_clk    [get_pins {n3xx_clocking_i/misc_clock_gen_i/inst/mmcm_adv_inst/CLKOUT0}]
+
+#*******************************************************************************
+## White Rabbit DAC
+# Constrain the DIN and NSYNC bits around the clock output. No readback.
+
+set WR_OUT_CLK [get_ports {WB_DAC_SCLK}]
+create_generated_clock -name wr_bus_clk \
+  -source [get_pins [all_fanin -flat -only_cells -startpoints_only $WR_OUT_CLK]/C] \
+  -divide_by 2 $WR_OUT_CLK
+
+#*******************************************************************************
+## Front Panel GPIO
+# These bits are driven from the DB-A radio clock. Although they are received async in
+# the outside world, they should be constrained in the FPGA to avoid any race
+# conditions. The best way to do this is a skew constraint across all the bits.
+
+set FP_GPIO_CLK [get_ports {FPGA_GPIO[0]}]
+create_generated_clock -name fp_gpio_bus_clk \
+  -source [get_pins [all_fanin -flat -only_cells -startpoints_only $FP_GPIO_CLK]/C] \
+  -divide_by 2 $FP_GPIO_CLK
+