diff options
| author | Alex Williams <alex.williams@ni.com> | 2020-01-28 16:08:20 -0800 | 
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2020-07-16 10:00:12 -0500 | 
| commit | d01e091c4c7ccc323d305580a27754918b02974b (patch) | |
| tree | 9ba5d3ea3f88bb420edebbea97837dd92bdff58b /fpga/usrp3/top/e320/dts/dma-common.dtsi | |
| parent | acafbd60558a7445e95671a8d0db6ad25b523056 (diff) | |
| download | uhd-d01e091c4c7ccc323d305580a27754918b02974b.tar.gz uhd-d01e091c4c7ccc323d305580a27754918b02974b.tar.bz2 uhd-d01e091c4c7ccc323d305580a27754918b02974b.zip  | |
e320: Swap out liberio for internal Ethernet
Diffstat (limited to 'fpga/usrp3/top/e320/dts/dma-common.dtsi')
| -rw-r--r-- | fpga/usrp3/top/e320/dts/dma-common.dtsi | 365 | 
1 files changed, 22 insertions, 343 deletions
diff --git a/fpga/usrp3/top/e320/dts/dma-common.dtsi b/fpga/usrp3/top/e320/dts/dma-common.dtsi index 0f3dde41d..d6671e16f 100644 --- a/fpga/usrp3/top/e320/dts/dma-common.dtsi +++ b/fpga/usrp3/top/e320/dts/dma-common.dtsi @@ -4,355 +4,34 @@   */  &fpga_full { -	tx_dma0: dma@43CA0000 { -		compatible = "adi,axi-dmac-1.00.a"; -		reg = <0x43CA0000 0x10000>; -		interrupts = <0 53 4>; +	nixge_internal: ethernet@40020000 { +		#address-cells = <1>; +		#size-cells = <1>; +		compatible = "ni,xge-enet-3.00"; +		reg = <0x40020000 0x4000 +		       0x40030000 0x2000>; +		reg-names = "dma", "ctrl"; +			clocks = <&clkc 15>; +			clock-names = "bus_clk"; + +		interrupts = <0 52 4>, <0 53 4>; +		interrupt-names = "rx", "tx";  		interrupt-parent = <&intc>; -		clocks = <&clkc 15>; -		#dma-cells = <1>; -		adi,channels { -			#size-cells = <0>; -			#address-cells = <1>; -			dma-channel@0 { -				reg = <0>; -				adi,source-bus-type = <0>; -				adi,source-bus-width = <0x20>; -				adi,destination-bus-type = <1>; -				adi,destination-bus-width = <0x20>; -				adi,length-width = <24>; -			}; -		}; -	}; -	tx_dma1: dma@43CB0000 { -		compatible = "adi,axi-dmac-1.00.a"; -		reg = <0x43CB0000 0x10000>; -		interrupts = <0 53 4>; -		interrupt-parent = <&intc>; -		clocks = <&clkc 15>; -		#dma-cells = <1>; -		adi,channels { -			#size-cells = <0>; -			#address-cells = <1>; -			dma-channel@0 { -				reg = <0>; -				adi,source-bus-type = <0>; -				adi,source-bus-width = <0x20>; -				adi,destination-bus-type = <1>; -				adi,destination-bus-width = <0x20>; -				adi,length-width = <24>; -			}; -		}; -	}; -	tx_dma2: dma@43CC0000 { -		compatible = "adi,axi-dmac-1.00.a"; -		reg = <0x43CC0000 0x10000>; -		interrupts = <0 53 4>; -		interrupt-parent = <&intc>; -		clocks = <&clkc 15>; -		#dma-cells = <1>; -		adi,channels { -			#size-cells = <0>; -			#address-cells = <1>; -			dma-channel@0 { -				reg = <0>; -				adi,source-bus-type = <0>; -				adi,source-bus-width = <0x20>; -				adi,destination-bus-type = <1>; -				adi,destination-bus-width = <0x20>; -				adi,length-width = <24>; -			}; -		}; -	}; -	tx_dma3: dma@43CD0000 { -		compatible = "adi,axi-dmac-1.00.a"; -		reg = <0x43CD0000 0x10000>; -		interrupts = <0 53 4>; -		interrupt-parent = <&intc>; -		clocks = <&clkc 15>; -		#dma-cells = <1>; -		adi,channels { -			#size-cells = <0>; -			#address-cells = <1>; -			dma-channel@0 { -				reg = <0>; -				adi,source-bus-type = <0>; -				adi,source-bus-width = <0x20>; -				adi,destination-bus-type = <1>; -				adi,destination-bus-width = <0x20>; -				adi,length-width = <24>; -			}; -		}; -	}; -	tx_dma4: dma@43CE0000 { -		compatible = "adi,axi-dmac-1.00.a"; -		reg = <0x43CE0000 0x10000>; -		interrupts = <0 53 4>; -		interrupt-parent = <&intc>; -		clocks = <&clkc 15>; -		#dma-cells = <1>; -		adi,channels { -			#size-cells = <0>; -			#address-cells = <1>; -			dma-channel@0 { -				reg = <0>; -				adi,source-bus-type = <0>; -				adi,source-bus-width = <0x20>; -				adi,destination-bus-type = <1>; -				adi,destination-bus-width = <0x20>; -				adi,length-width = <24>; -			}; -		}; -	}; -	tx_dma5: dma@43CF0000 { -		compatible = "adi,axi-dmac-1.00.a"; -		reg = <0x43CF0000 0x10000>; -		interrupts = <0 53 4>; -		interrupt-parent = <&intc>; -		clocks = <&clkc 15>; -		#dma-cells = <1>; -		adi,channels { -			#size-cells = <0>; -			#address-cells = <1>; -			dma-channel@0 { -				reg = <0>; -				adi,source-bus-type = <0>; -				adi,source-bus-width = <0x20>; -				adi,destination-bus-type = <1>; -				adi,destination-bus-width = <0x20>; -				adi,length-width = <24>; -			}; -		}; -	}; -	rx_dma0: dma@43C00000 { -		compatible = "adi,axi-dmac-1.00.a"; -		reg = <0x43C00000 0x10000>; -		interrupts = <0 52 4>; -		interrupt-parent = <&intc>; -		clocks = <&clkc 15>; -		#dma-cells = <1>; -		adi,channels { -			#size-cells = <0>; -			#address-cells = <1>; -			dma-channel@0 { -				reg = <0>; -				adi,source-bus-type = <1>; -				adi,source-bus-width = <0x20>; -				adi,destination-bus-type = <0>; -				adi,destination-bus-width = <0x20>; -				adi,length-width = <24>; -			}; -		}; -	}; -	rx_dma1: dma@43C10000 { -		compatible = "adi,axi-dmac-1.00.a"; -		reg = <0x43C10000 0x10000>; -		interrupts = <0 52 4>; -		interrupt-parent = <&intc>; -		clocks = <&clkc 15>; -		#dma-cells = <1>; -		adi,channels { -			#size-cells = <0>; -			#address-cells = <1>; -			dma-channel@0 { -				reg = <0>; -				adi,source-bus-type = <1>; -				adi,source-bus-width = <0x20>; -				adi,destination-bus-type = <0>; -				adi,destination-bus-width = <0x20>; -				adi,length-width = <24>; -			}; -		}; -	}; -	rx_dma2: dma@43C20000 { -		compatible = "adi,axi-dmac-1.00.a"; -		reg = <0x43C20000 0x10000>; -		interrupts = <0 52 4>; -		interrupt-parent = <&intc>; -		clocks = <&clkc 15>; -		#dma-cells = <1>; -		adi,channels { -			#size-cells = <0>; -			#address-cells = <1>; -			dma-channel@0 { -				reg = <0>; -				adi,source-bus-type = <1>; -				adi,source-bus-width = <0x20>; -				adi,destination-bus-type = <0>; -				adi,destination-bus-width = <0x20>; -				adi,length-width = <24>; -			}; -		}; -	}; -	rx_dma3: dma@43C30000 { -		compatible = "adi,axi-dmac-1.00.a"; -		reg = <0x43C30000 0x10000>; -		interrupts = <0 52 4>; -		interrupt-parent = <&intc>; -		clocks = <&clkc 15>; -		#dma-cells = <1>; -		adi,channels { -			#size-cells = <0>; -			#address-cells = <1>; -			dma-channel@0 { -				reg = <0>; -				adi,source-bus-type = <1>; -				adi,source-bus-width = <0x20>; -				adi,destination-bus-type = <0>; -				adi,destination-bus-width = <0x20>; -				adi,length-width = <24>; -			}; -		}; -	}; -	rx_dma4: dma@43C40000 { -		compatible = "adi,axi-dmac-1.00.a"; -		reg = <0x43C40000 0x10000>; -		interrupts = <0 52 4>; -		interrupt-parent = <&intc>; -		clocks = <&clkc 15>; -		#dma-cells = <1>; -		adi,channels { -			#size-cells = <0>; -			#address-cells = <1>; -			dma-channel@0 { -				reg = <0>; -				adi,source-bus-type = <1>; -				adi,source-bus-width = <0x20>; -				adi,destination-bus-type = <0>; -				adi,destination-bus-width = <0x20>; -				adi,length-width = <24>; -			}; -		}; -	}; -	rx_dma5: dma@43C50000 { -		compatible = "adi,axi-dmac-1.00.a"; -		reg = <0x43C50000 0x10000>; -		interrupts = <0 52 4>; -		interrupt-parent = <&intc>; -		clocks = <&clkc 15>; -		#dma-cells = <1>; -		adi,channels { -			#size-cells = <0>; -			#address-cells = <1>; -			dma-channel@0 { -				reg = <0>; -				adi,source-bus-type = <1>; -				adi,source-bus-width = <0x20>; -				adi,destination-bus-type = <0>; -				adi,destination-bus-width = <0x20>; -				adi,length-width = <24>; -			}; -		}; -	}; - -	usrp_rx_dma0: usrp-rx-dma@43c00000 { -		compatible = "ettus,usrp-rx-dma"; -		dmas = <&rx_dma0 0>; -		dma-names = "dma"; -		port-id = <0>; -		status = "okay"; - -		regmap = <&dma_conf0>; -		offset = <0x0>; -	}; - -	usrp_rx_dma1: usrp-rx-dma@43c10000 { -		compatible = "ettus,usrp-rx-dma"; -		dmas = <&rx_dma1 0>; -		dma-names = "dma"; -		port-id = <1>; - -		regmap = <&dma_conf0>; -		offset = <0x4>; -	}; - -	usrp_rx_dma2: usrp-rx-dma@43c20000 { -		compatible = "ettus,usrp-rx-dma"; -		dmas = <&rx_dma2 0>; -		dma-names = "dma"; -		port-id = <2>; - -		regmap = <&dma_conf0>; -		offset = <0x8>; -	}; - -	usrp_rx_dma3: usrp-rx-dma@43c30000 { -		compatible = "ettus,usrp-rx-dma"; -		dmas = <&rx_dma3 0>; -		dma-names = "dma"; -		port-id = <3>; - -		regmap = <&dma_conf0>; -		offset = <0xc>; -	}; - -	usrp_rx_dma4: usrp-rx-dma@43c40000 { -		compatible = "ettus,usrp-rx-dma"; -		dmas = <&rx_dma4 0>; -		dma-names = "dma"; -		port-id = <4>; - -		regmap = <&dma_conf0>; -		offset = <0x10>; -	}; - -	usrp_rx_dma5: usrp-rx-dma@43c50000 { -		compatible = "ettus,usrp-rx-dma"; -		dmas = <&rx_dma5 0>; -		dma-names = "dma"; -		port-id = <5>; - -		regmap = <&dma_conf0>; -		offset = <0x14>; -	}; - -	usrp_tx_dma0: usrp-tx-dma@43ca0000 { -		compatible = "ettus,usrp-tx-dma"; -		dmas = <&tx_dma0 0>; -		dma-names = "dma"; -		port-id = <0>; -	}; - -	usrp_tx_dma1: usrp-tx-dma@43cb0000 { -		compatible = "ettus,usrp-tx-dma"; -		dmas = <&tx_dma1 0>; -		dma-names = "dma"; -		port-id = <1>; -	}; - -	usrp_tx_dma2: usrp-tx-dma@43cc0000 { -		compatible = "ettus,usrp-tx-dma"; -		dmas = <&tx_dma2 0>; -		dma-names = "dma"; -		port-id = <2>;  		status = "okay"; -	}; - -	usrp_tx_dma3: usrp-tx-dma@43cd0000 { -		compatible = "ettus,usrp-tx-dma"; -		dmas = <&tx_dma3 0>; -		dma-names = "dma"; -		port-id = <3>; -	}; -	usrp_tx_dma4: usrp-tx-dma@43ce0000 { -		compatible = "ettus,usrp-tx-dma"; -		dmas = <&tx_dma4 0>; -		dma-names = "dma"; -		port-id = <4>; -		status = "okay"; -	}; +		phy-mode = "internal"; +		local-mac-address = <0x00 0x01 0x02 0x03 0x04 0x05>; -	usrp_tx_dma5: usrp-tx-dma@43cf0000 { -		compatible = "ettus,usrp-tx-dma"; -		dmas = <&tx_dma5 0>; -		dma-names = "dma"; -		port-id = <5>; +		fixed-link { +			speed = <1000>; +			full-duplex; +		};  	}; -	dma_conf0: dma_conf0@42080000 { -		compatible = "syscon"; -		reg = <0x42080000 0x1000>; +	uio@40032000 { +		compatible = "usrp-uio"; +		reg = <0x40032000 0x2000>; +		reg-names = "misc-enet-int-regs";  		status = "okay";  	};  };  | 
