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| author | Michael West <michael.west@ettus.com> | 2013-12-06 17:47:24 -0800 |
|---|---|---|
| committer | Michael West <michael.west@ettus.com> | 2013-12-06 17:47:24 -0800 |
| commit | c3aa7326095a1a8c744e269a04572de74600df8d (patch) | |
| tree | 983711ae9718128617b5f1880f8c6399e38e4055 /fpga/usrp3/top/b200/timing.ucf | |
| parent | aa3d9a9da0405e84e720870a13718b177d85652c (diff) | |
| parent | 8f0f045cdac16ae84bc446b230beb2b651428294 (diff) | |
| download | uhd-c3aa7326095a1a8c744e269a04572de74600df8d.tar.gz uhd-c3aa7326095a1a8c744e269a04572de74600df8d.tar.bz2 uhd-c3aa7326095a1a8c744e269a04572de74600df8d.zip | |
Merge branch 'master' into mwest_coverity
Conflicts:
host/lib/usrp/b200/b200_iface.cpp
Diffstat (limited to 'fpga/usrp3/top/b200/timing.ucf')
| -rw-r--r-- | fpga/usrp3/top/b200/timing.ucf | 41 |
1 files changed, 23 insertions, 18 deletions
diff --git a/fpga/usrp3/top/b200/timing.ucf b/fpga/usrp3/top/b200/timing.ucf index e21d4cb1a..4b7817134 100644 --- a/fpga/usrp3/top/b200/timing.ucf +++ b/fpga/usrp3/top/b200/timing.ucf @@ -20,21 +20,26 @@ TIMESPEC "TS_codec_data_clk_p" = PERIOD "codec_data_clk_p" 16276 ps HIGH 50 %; INST "GPIF_*" IOB = TRUE; #low speed misc output group -INST "SFDX*" TNM = ls_misc_out; -INST "SRX*" TNM = ls_misc_out; -INST "LED_*" TNM = ls_misc_out; -INST "tx_enable*" TNM = ls_misc_out; -INST "tx_bandsel_*" TNM = ls_misc_out; -INST "rx_bandsel_*" TNM = ls_misc_out; -INST "ref_sel" TNM = ls_misc_out; -INST "*_ce" TNM = ls_misc_out; -INST "*_miso" TNM = ls_misc_out; -INST "*_mosi" TNM = ls_misc_out; -INST "*_sclk" TNM = ls_misc_out; -INST "gps_*" TNM = ls_misc_out; -INST "FPGA_*D0" TNM = ls_misc_out; - -#constrain the misc IOs to the bus clock -NET "bus_clk" TNM_NET = "bus_clk"; -TIMESPEC "TS_bus_clk" = PERIOD "bus_clk" 10 ns HIGH 50 %; -TIMEGRP "ls_misc_out" OFFSET = OUT 15 ns AFTER "bus_clk" RISING; +INST "SFDX*" TNM = radio_misc_out; # Radio Clk domain +INST "SRX*" TNM = radio_misc_out; # Radio Clk domain +INST "LED_*" TNM = radio_misc_out; # Radio Clk domain +INST "tx_enable*" TNM = radio_misc_out; # Radio Clk domain +INST "tx_bandsel_*" TNM = ls_misc_out; # Bus clk domain +INST "rx_bandsel_*" TNM = ls_misc_out; # Bus clk domain +INST "ref_sel" TNM = ls_misc_out; # Bus clk domain +INST "pll_ce" TNM = ls_misc_out; # Bus clk domain +INST "cat_ce" TNM = ls_misc_out; # Bus clk domain + combinatorial +#INST "fx3_miso" TNM = ls_misc_out; # Combinatorial +INST "cat_miso" TNM = ls_misc_out; # Bus clk domain (I) +INST "cat_mosi" TNM = ls_misc_out; # Bus clk domain + combinatorial +INST "pll_mosi" TNM = ls_misc_out; # Bus clk domain + combinatorial +INST "*_sclk" TNM = ls_misc_out; # Bus clk domain + combinatorial +INST "gps_*" TNM = ls_misc_out; # Bus clk domain +#INST "FPGA_*D0" TNM = ls_misc_out; # UNUSED + +#constrain the misc IOs to the clocks +NET "gpif_clk" TNM_NET = "gpif_clk"; +TIMESPEC "TS_gpif_clk" = PERIOD "gpif_clk" 10 ns HIGH 50 %; +TIMEGRP "ls_misc_out" OFFSET = OUT 15 ns AFTER "gpif_clk" RISING; +TIMEGRP "radio_misc_out" OFFSET = OUT 15 ns AFTER "radio_clk" RISING; + |