Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

1 files changed, 149 insertions, 0 deletions

diff --git a/fpga/usrp3/tools/scripts/viv_sim_project.tcl b/fpga/usrp3/tools/scripts/viv_sim_project.tcl
new file mode 100644
index 000000000..f2d071f10
--- /dev/null
+++ b/fpga/usrp3/tools/scripts/viv_sim_project.tcl
@@ -0,0 +1,149 @@
+#
+# Copyright 2014 Ettus Research
+#
+
+# ---------------------------------------
+# Gather all external parameters
+# ---------------------------------------
+set simulator       $::env(VIV_SIMULATOR)
+set design_srcs     $::env(VIV_DESIGN_SRCS)
+set sim_srcs        $::env(VIV_SIM_SRCS)
+set inc_srcs        $::env(VIV_INC_SRCS)
+set sim_top         $::env(VIV_SIM_TOP)
+set part_name       $::env(VIV_PART_NAME)
+set sim_runtime     $::env(VIV_SIM_RUNTIME)
+set sim_fast        $::env(VIV_SIM_FAST)
+set vivado_mode     $::env(VIV_MODE)
+set working_dir     [pwd]
+
+set sim_fileset "sim_1"
+set project_name "[string tolower $simulator]_proj"
+
+if [info exists ::env(VIV_SIM_COMPLIBDIR) ] {
+    set sim_complibdir  $::env(VIV_SIM_COMPLIBDIR)
+    if [expr [file isdirectory $sim_complibdir] == 0] {
+        set sim_complibdir  ""
+    }
+} else {
+    set sim_complibdir  ""
+}
+if [expr ([string equal $simulator "XSim"] == 0) && ([string length $sim_complibdir] == 0)] {
+    puts "BUILDER: \[ERROR\]: Could not resolve the location for the compiled simulation libraries."
+    puts "                  Please build libraries for chosen simulator and set the env or"
+    puts "                  makefile variable SIM_COMPLIBDIR to point to the location."
+    exit 1
+}
+
+# ---------------------------------------
+# Vivado Commands
+# ---------------------------------------
+puts "BUILDER: Creating Vivado simulation project part $part_name"
+create_project -part $part_name -force $project_name/$project_name
+
+foreach src_file $design_srcs {
+    set src_ext [file extension $src_file ]
+    if [expr [lsearch {.vhd .vhdl} $src_ext] >= 0] {
+        puts "BUILDER: Adding VHDL    : $src_file"
+        read_vhdl $src_file
+    } elseif [expr [lsearch {.v .vh} $src_ext] >= 0] {
+        puts "BUILDER: Adding Verilog : $src_file"
+        read_verilog $src_file
+    } elseif [expr [lsearch {.sv .svh} $src_ext] >= 0] {
+        puts "BUILDER: Adding SVerilog: $src_file"
+        read_verilog -sv $src_file
+    } elseif [expr [lsearch {.xdc} $src_ext] >= 0] {
+        puts "BUILDER: Adding XDC     : $src_file"
+        read_xdc $src_file
+    } elseif [expr [lsearch {.xci} $src_ext] >= 0] {
+        puts "BUILDER: Adding IP      : $src_file"
+        read_ip $src_file
+    } elseif [expr [lsearch {.ngc .edif} $src_ext] >= 0] {
+        puts "BUILDER: Adding Netlist : $src_file"
+        read_edif $src_file
+    } elseif [expr [lsearch {.bd} $src_ext] >= 0] {
+            puts "BUILDER: Adding Block Diagram: $src_file"
+            add_files -norecurse $src_file
+    } elseif [expr [lsearch {.bxml} $src_ext] >= 0] {
+            puts "BUILDER: Adding Block Diagram XML: $src_file"
+            add_files -norecurse $src_file
+    } else {
+        puts "BUILDER: \[WARNING\] File ignored!!!: $src_file"
+    }
+}
+
+foreach sim_src $sim_srcs {
+    puts "BUILDER: Adding Sim Src : $sim_src"
+    add_files -fileset $sim_fileset -norecurse $sim_src
+}
+
+foreach inc_src $inc_srcs {
+    puts "BUILDER: Adding Inc Src : $inc_src"
+    add_files -fileset $sim_fileset -norecurse $inc_src
+}
+
+# Simulator independent config
+set_property top $sim_top [get_filesets $sim_fileset]
+set_property default_lib xil_defaultlib [current_project]
+update_compile_order -fileset sim_1 -quiet
+
+# Select the simulator
+# WARNING: Do this first before setting simulator specific properties!
+set_property target_simulator $simulator [current_project]
+
+# Vivado quirk when passing options to external simulators
+if [expr [string equal $simulator "XSim"] == 1] {
+    set_property verilog_define "WORKING_DIR=\"$working_dir\"" [get_filesets $sim_fileset]
+} else {
+    set_property verilog_define "WORKING_DIR=$working_dir" [get_filesets $sim_fileset]
+}
+
+# XSim specific settings
+set_property xsim.simulate.runtime "${sim_runtime}us" -objects [get_filesets $sim_fileset]
+set_property xsim.elaborate.debug_level "all" -objects [get_filesets $sim_fileset]
+set_property xsim.elaborate.unifast $sim_fast -objects [get_filesets $sim_fileset]
+# Set default timescale to prevent bogus warnings
+set_property xsim.elaborate.xelab.more_options -value {-timescale 1ns/1ns} -objects [get_filesets $sim_fileset]
+
+# Modelsim specific settings
+if [expr [string equal $simulator "Modelsim"] == 1] {
+    set sim_64bit       $::env(VIV_SIM_64BIT)
+
+    set_property compxlib.modelsim_compiled_library_dir $sim_complibdir [current_project]
+    # Does not work yet (as of Vivado 2015.2), but will be useful for 32-bit support
+    # See: http://www.xilinx.com/support/answers/62210.html
+    set_property modelsim.64bit $sim_64bit -objects [get_filesets $sim_fileset]
+    set_property modelsim.simulate.runtime "${sim_runtime}ns" -objects [get_filesets $sim_fileset]
+    set_property modelsim.elaborate.acc "true" -objects [get_filesets $sim_fileset]
+    set_property modelsim.simulate.log_all_signals "true" -objects [get_filesets $sim_fileset]
+    set_property modelsim.simulate.vsim.more_options -value "-c" -objects [get_filesets $sim_fileset]
+    set_property modelsim.elaborate.unifast $sim_fast -objects [get_filesets $sim_fileset]
+    if [info exists ::env(VIV_SIM_USER_DO) ] {
+        set_property modelsim.simulate.custom_udo -value "$::env(VIV_SIM_USER_DO)" -objects [get_filesets $sim_fileset]
+    }
+}
+
+# Launch simulation
+launch_simulation
+
+# Synthesize requested modules
+foreach synth_top "$::env(VIV_SYNTH_TOP)" {
+    set_property top $synth_top [current_fileset]
+    synth_design -mode out_of_context
+    # Perform a simple regex-based search for all clock signals and constrain
+    # them to 500 MHz for the timing report.
+    set clk_regexp "(?i)^(?!.*en.*).*(clk|clock).*"
+    foreach clk_inst [get_ports -regexp $clk_regexp] {
+      create_clock -name $clk_inst -period 2.0 [get_ports $clk_inst]
+    }
+    report_utilization -no_primitives -file ${working_dir}/${synth_top}_synth.rpt
+    report_timing_summary -setup -max_paths 3 -unique_pins -no_header -append -file ${working_dir}/${synth_top}_synth.rpt
+    write_checkpoint -force ${working_dir}/${synth_top}_synth.dcp
+}
+
+# Close project
+if [string equal $vivado_mode "batch"] {
+    puts "BUILDER: Closing project"
+    close_project
+} else {
+    puts "BUILDER: In GUI mode. Leaving project open."
+}