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| author | Martin Braun <martin.braun@ettus.com> | 2020-12-01 18:50:12 +0100 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2021-01-04 13:28:36 -0600 |
| commit | ca68195b5d12c5410cfac8d459a0b0902c4c72c7 (patch) | |
| tree | d50d2bd7541000fa0a0470c4f1f4610c93d3b410 /fpga/usrp3/tools/make/viv_design_builder.mak | |
| parent | 3b9ced8f07c068faf1f494ce170cb44edaa47075 (diff) | |
| download | uhd-ca68195b5d12c5410cfac8d459a0b0902c4c72c7.tar.gz uhd-ca68195b5d12c5410cfac8d459a0b0902c4c72c7.tar.bz2 uhd-ca68195b5d12c5410cfac8d459a0b0902c4c72c7.zip | |
fpga: Remove Python2 support from build system
- 2to3 was used to convert the Python scripts, except where the tool
choked and manual intervention was required
- All references to "python" where replaced with "python3"
- buffer() was replaced by memoryview()
Diffstat (limited to 'fpga/usrp3/tools/make/viv_design_builder.mak')
| -rw-r--r-- | fpga/usrp3/tools/make/viv_design_builder.mak | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/fpga/usrp3/tools/make/viv_design_builder.mak b/fpga/usrp3/tools/make/viv_design_builder.mak index 5a54da012..74f1ef034 100644 --- a/fpga/usrp3/tools/make/viv_design_builder.mak +++ b/fpga/usrp3/tools/make/viv_design_builder.mak @@ -22,7 +22,7 @@ BUILD_VIVADO_DESIGN = \ export VIV_TOOLS_DIR=$(call RESOLVE_PATH,$(TOOLS_DIR)); \ export VIV_OUTPUT_DIR=$(call RESOLVE_PATH,$(BUILD_DIR)); \ export VIV_TOP_MODULE=$(2); \ - export VIV_PART_NAME=`python $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \ + export VIV_PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \ export VIV_MODE=$(VIVADO_MODE); \ export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(DESIGN_SRCS)); \ export VIV_VERILOG_DEFS="$(VERILOG_DEFS)"; \ @@ -47,7 +47,7 @@ CHECK_VIVADO_DESIGN = \ export VIV_TOOLS_DIR=$(call RESOLVE_PATH,$(TOOLS_DIR)); \ export VIV_OUTPUT_DIR=$(call RESOLVE_PATH,$(BUILD_DIR)); \ export VIV_TOP_MODULE=$(2); \ - export VIV_PART_NAME=`python $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \ + export VIV_PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \ export VIV_MODE=$(VIVADO_MODE); \ export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(DESIGN_SRCS)); \ export VIV_VERILOG_DEFS="$(VERILOG_DEFS)"; \ |