Removed copy of FPGA source files.

4 files changed, 0 insertions, 212 deletions

diff --git a/fpga/usrp3/sim/serial_to_settings/serial_settings_tasks.v b/fpga/usrp3/sim/serial_to_settings/serial_settings_tasks.v
deleted file mode 100644
index a9e2c0344..000000000
--- a/fpga/usrp3/sim/serial_to_settings/serial_settings_tasks.v
+++ /dev/null
@@ -1,59 +0,0 @@
-
-   task serial_settings_transaction;
-      input [7:0] address;
-      input [31:0] data;
-
-      integer x;
-      
-      begin
-	 scl_r <= 1'b1;
-	 sda_r <= 1'b1;
-	 @(negedge clk);
-	 @(negedge clk);
-	 // Drive SDA low whilst SCL high to signal START
-	 sda_r <= 1'b0;
-	 @(negedge clk);
-	 @(negedge clk);
-	 // Send 8 Address bits MSB first on falling edge of SCL clocks
-	 for (x = 7; x >= 0; x = x - 1)
-	   serial_settings_bit(address[x]);
-	 // Send 32 Data bits MSB first on falling edge of SCL clocks
-	 for (x = 31; x >= 0; x = x - 1)
-	   serial_settings_bit(data[x]);
-	 // Send STOP.
-	 scl_r <= 1'b0;
-	 sda_r <= 1'b0;
-	  @(negedge clk);
-	 @(negedge clk);
-	 @(negedge clk);
-	 @(negedge clk);
-	 scl_r <= 1'b1;
-	 @(negedge clk);	 
-	 @(negedge clk);
-	 @(negedge clk);	
-	 @(negedge clk);
-	 sda_r <= 1'b1;
-	 @(negedge clk);	 
-	 @(negedge clk);
-	 @(negedge clk);	
-	 @(negedge clk);
-      end
-   endtask // serial_settings_transaction
-
-   task serial_settings_bit;
-      input one_bit;
-
-      begin
-	 scl_r <= 1'b0;
-	 sda_r <= one_bit;
-	 @(negedge clk);
-	 @(negedge clk);
-	 @(negedge clk);
-	 @(negedge clk);
-	 scl_r <= 1'b1;
-	 @(negedge clk);	 
-	 @(negedge clk);
-	 @(negedge clk);	
-	 @(negedge clk);
-      end
-   endtask // send_settings_bit
diff --git a/fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/default.wcfg b/fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/default.wcfg
deleted file mode 100644
index 877ce2f20..000000000
--- a/fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/default.wcfg
+++ /dev/null
@@ -1,86 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<wave_config>
-   <wave_state>
-   </wave_state>
-   <db_ref_list>
-      <db_ref path="./isim.wdb" id="1" type="auto">
-         <top_modules>
-            <top_module name="glbl" />
-            <top_module name="serial_to_settings_tb" />
-         </top_modules>
-      </db_ref>
-   </db_ref_list>
-   <WVObjectSize size="17" />
-   <wvobject fp_name="/serial_to_settings_tb/clk" type="logic" db_ref_id="1">
-      <obj_property name="ElementShortName">clk</obj_property>
-      <obj_property name="ObjectShortName">clk</obj_property>
-   </wvobject>
-   <wvobject fp_name="/serial_to_settings_tb/reset" type="logic" db_ref_id="1">
-      <obj_property name="ElementShortName">reset</obj_property>
-      <obj_property name="ObjectShortName">reset</obj_property>
-   </wvobject>
-   <wvobject fp_name="/serial_to_settings_tb/scl_r" type="logic" db_ref_id="1">
-      <obj_property name="ElementShortName">scl_r</obj_property>
-      <obj_property name="ObjectShortName">scl_r</obj_property>
-   </wvobject>
-   <wvobject fp_name="/serial_to_settings_tb/sda_r" type="logic" db_ref_id="1">
-      <obj_property name="ElementShortName">sda_r</obj_property>
-      <obj_property name="ObjectShortName">sda_r</obj_property>
-   </wvobject>
-   <wvobject fp_name="/serial_to_settings_tb/scl" type="logic" db_ref_id="1">
-      <obj_property name="ElementShortName">scl</obj_property>
-      <obj_property name="ObjectShortName">scl</obj_property>
-   </wvobject>
-   <wvobject fp_name="/serial_to_settings_tb/sda" type="logic" db_ref_id="1">
-      <obj_property name="ElementShortName">sda</obj_property>
-      <obj_property name="ObjectShortName">sda</obj_property>
-   </wvobject>
-   <wvobject fp_name="/serial_to_settings_tb/set_stb" type="logic" db_ref_id="1">
-      <obj_property name="ElementShortName">set_stb</obj_property>
-      <obj_property name="ObjectShortName">set_stb</obj_property>
-   </wvobject>
-   <wvobject fp_name="/serial_to_settings_tb/set_addr" type="array" db_ref_id="1">
-      <obj_property name="ElementShortName">set_addr[7:0]</obj_property>
-      <obj_property name="ObjectShortName">set_addr[7:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-   </wvobject>
-   <wvobject fp_name="/serial_to_settings_tb/set_data" type="array" db_ref_id="1">
-      <obj_property name="ElementShortName">set_data[31:0]</obj_property>
-      <obj_property name="ObjectShortName">set_data[31:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-   </wvobject>
-   <wvobject fp_name="/serial_to_settings_tb/serial_to_settings_i/state" type="array" db_ref_id="1">
-      <obj_property name="ElementShortName">state[2:0]</obj_property>
-      <obj_property name="ObjectShortName">state[2:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-   </wvobject>
-   <wvobject fp_name="/serial_to_settings_tb/serial_to_settings_i/scl_pre_reg" type="logic" db_ref_id="1">
-      <obj_property name="ElementShortName">scl_pre_reg</obj_property>
-      <obj_property name="ObjectShortName">scl_pre_reg</obj_property>
-   </wvobject>
-   <wvobject fp_name="/serial_to_settings_tb/serial_to_settings_i/scl_reg" type="logic" db_ref_id="1">
-      <obj_property name="ElementShortName">scl_reg</obj_property>
-      <obj_property name="ObjectShortName">scl_reg</obj_property>
-   </wvobject>
-   <wvobject fp_name="/serial_to_settings_tb/serial_to_settings_i/scl_reg2" type="logic" db_ref_id="1">
-      <obj_property name="ElementShortName">scl_reg2</obj_property>
-      <obj_property name="ObjectShortName">scl_reg2</obj_property>
-   </wvobject>
-   <wvobject fp_name="/serial_to_settings_tb/serial_to_settings_i/sda_pre_reg" type="logic" db_ref_id="1">
-      <obj_property name="ElementShortName">sda_pre_reg</obj_property>
-      <obj_property name="ObjectShortName">sda_pre_reg</obj_property>
-   </wvobject>
-   <wvobject fp_name="/serial_to_settings_tb/serial_to_settings_i/sda_reg" type="logic" db_ref_id="1">
-      <obj_property name="ElementShortName">sda_reg</obj_property>
-      <obj_property name="ObjectShortName">sda_reg</obj_property>
-   </wvobject>
-   <wvobject fp_name="/serial_to_settings_tb/serial_to_settings_i/sda_reg2" type="logic" db_ref_id="1">
-      <obj_property name="ElementShortName">sda_reg2</obj_property>
-      <obj_property name="ObjectShortName">sda_reg2</obj_property>
-   </wvobject>
-   <wvobject fp_name="/serial_to_settings_tb/serial_to_settings_i/counter" type="array" db_ref_id="1">
-      <obj_property name="ElementShortName">counter[4:0]</obj_property>
-      <obj_property name="ObjectShortName">counter[4:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-   </wvobject>
-</wave_config>
diff --git a/fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/run_isim b/fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/run_isim
deleted file mode 100755
index e4730676b..000000000
--- a/fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/run_isim
+++ /dev/null
@@ -1,24 +0,0 @@
-vlogcomp -work work ${XILINX}/verilog/src/glbl.v
-
-vlogcomp -work work --sourcelibext .v \
-	 --sourcelibdir ../../../lib/axi \
-	 --sourcelibdir ../../../lib/fifo \
-         --sourcelibdir ../../../lib/control \
-	 --sourcelibdir ../../../top/b200/coregen \
-	 --sourcelibdir ../../../top/b200 \
-        --sourcelibdir ../../../lib/timing \
-        --sourcelibdir ../../../lib/vita \
-        --sourcelibdir ../../../lib/packet_proc \
-        --sourcelibdir ../../../lib/dsp \
-        --sourcelibdir ../../../lib/wishbone \
-        --sourcelibdir ../../../lib/gpif2 \
-	 ../../../lib/control/serial_to_settings_tb.v
-
-
-
-fuse  work.serial_to_settings_tb work.glbl  -L unisims_ver -L xilinxcorelib_ver -o serial_to_settings_tb.exe
-
-# run the simulation scrip
-./serial_to_settings_tb.exe   -gui #-tclbatch simcmds.tcl
-
-
diff --git a/fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/simulation_script.v b/fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/simulation_script.v
deleted file mode 100644
index d3b669594..000000000
--- a/fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/simulation_script.v
+++ /dev/null
@@ -1,43 +0,0 @@
-
-`include "../serial_settings_tasks.v"
-
-   initial 
-     begin
-	clk <= 1'b0;
-	reset <= 1'b0;
-	scl_r <= 1'b1;
-	sda_r <= 1'b1;
-     end
-   
-   always
-     #5 clk <= ~clk;
-   
-   initial
-     begin
-
-	
-	@(negedge clk);
-	reset <= 1'b1;
-	repeat(10) @(negedge clk);
-	reset <= 1'b0;
-	repeat(10) @(negedge clk);
-
-	serial_settings_transaction(8'h0,32'h01b2);
-
-	serial_settings_transaction(8'h3, 32'h5);
-	
-	serial_settings_transaction(8'h3,32'hA);
-	
-	serial_settings_transaction(8'h3,32'hF);
-	
-	
-	repeat(10000) @(negedge clk);	 
-	@(negedge clk);
-	@(negedge clk);	
-	@(negedge clk);
-
-	$finish;
-	
-     end // initial begin
-
-	 
\ No newline at end of file