Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

1 files changed, 231 insertions, 0 deletions

diff --git a/fpga/usrp3/lib/zynq_fifo/zf_arbiter.v b/fpga/usrp3/lib/zynq_fifo/zf_arbiter.v
new file mode 100644
index 000000000..8a6bc7778
--- /dev/null
+++ b/fpga/usrp3/lib/zynq_fifo/zf_arbiter.v
@@ -0,0 +1,231 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Copyright Ettus Research LLC
+// Copyright 2014 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// The ZYNQ FIFO configuration arbiter:
+//  - holds configuration memory addresses
+//  - setting and readback for slave state machines
+//  - stream of memory addresses for master state machines
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module zf_arbiter
+#(
+    parameter STREAMS_WIDTH = 2,
+    parameter CMDFIFO_DEPTH = 4,
+    parameter PAGE_WIDTH = 16,
+    parameter USE_INT_STREAM_SEL = 0    // Use internal round robin stream selection
+)
+(
+    input clk,
+    input rst,
+
+    //------------------------------------------------------------------
+    //-- settings interface
+    //------------------------------------------------------------------
+    input [31:0] set_addr,
+    input [31:0] set_data,
+    input set_stb,
+
+    //------------------------------------------------------------------
+    //-- readback interface
+    //------------------------------------------------------------------
+    input [31:0] rb_addr,
+    output [31:0] rb_data,
+    input rb_stb,
+
+    //------------------------------------------------------------------
+    //-- fifo interactive interface
+    //------------------------------------------------------------------
+    output [71:0] cmd_tdata,
+    output cmd_tvalid,
+    input cmd_tready,
+    input [7:0] sts_tdata,
+    input sts_tvalid,
+    output sts_tready,
+
+    //------------------------------------------------------------------
+    //-- which stream to process? externally provided if USE_INT_STREAM_SEL = 0
+    //------------------------------------------------------------------
+    input [STREAMS_WIDTH-1:0] ext_stream_sel,
+    input ext_stream_valid,
+
+    output [31:0] debug
+);
+
+////////////////////////////////////////////////////////////////////////
+///////////////////////////// Begin R T L //////////////////////////////
+////////////////////////////////////////////////////////////////////////
+
+    localparam NUM_STREAMS = (1 << STREAMS_WIDTH);
+
+    reg [STREAMS_WIDTH-1:0] which_stream;
+
+    //readback mux assignment
+    reg [31:0] rb_data_i [NUM_STREAMS-1:0];
+    assign rb_data = rb_data_i[rb_addr[STREAMS_WIDTH+4:5]];
+
+    //cmd + sts fifo mux signals
+    wire [72:0] cmd_data_i [NUM_STREAMS-1:0];
+    assign cmd_tdata = cmd_data_i[which_stream];
+    wire cmd_tvalid_i [NUM_STREAMS-1:0];
+    wire sts_tready_i [NUM_STREAMS-1:0];
+
+    ////////////////////////////////////////////////////////////////////
+    // state machine for driving fifo arbitration
+    ////////////////////////////////////////////////////////////////////
+    localparam STATE_SET_WHICH_STREAM = 0;
+    localparam STATE_ASSERT_DO_CMD = 1;
+    localparam STATE_ASSERT_DO_STS = 2;
+    localparam STATE_SOME_IDLE = 3;
+
+    reg [1:0] state;
+
+    wire [STREAMS_WIDTH-1:0] stream_sel;
+    wire stream_valid;
+
+    generate
+    if (USE_INT_STREAM_SEL) begin
+        reg [STREAMS_WIDTH-1:0] int_stream_sel;
+        always @(posedge clk) begin
+            if (rst) begin
+                int_stream_sel <= 0;
+            end else begin
+                if (state == STATE_SET_WHICH_STREAM) begin
+                    if (int_stream_sel < NUM_STREAMS-1) begin
+                        int_stream_sel <= int_stream_sel + 1;
+                    end else begin
+                        int_stream_sel <= 0;
+                    end
+                end
+            end
+        end
+        assign stream_sel = int_stream_sel;
+        assign stream_valid = 1'b1;
+    end else begin
+        assign stream_sel = ext_stream_sel;
+        assign stream_valid = ext_stream_valid;
+    end
+    endgenerate
+
+    always @(posedge clk) begin
+        if (rst) begin
+            state <= STATE_SET_WHICH_STREAM;
+            which_stream <= 0;
+        end
+        else case (state)
+
+        STATE_SET_WHICH_STREAM: begin
+            if (cmd_tvalid_i[stream_sel]) state <= STATE_ASSERT_DO_CMD;
+            which_stream <= stream_sel;
+        end
+
+        STATE_ASSERT_DO_CMD: begin
+            if (cmd_tvalid && cmd_tready) state <= STATE_ASSERT_DO_STS;
+        end
+
+        STATE_ASSERT_DO_STS: begin
+            if (sts_tvalid && sts_tready) state <= STATE_SOME_IDLE;
+        end
+
+        STATE_SOME_IDLE: begin
+            state <= STATE_SET_WHICH_STREAM;
+        end
+
+        default: state <= STATE_SET_WHICH_STREAM;
+
+        endcase //state
+    end
+
+    ////////////////////////////////////////////////////////////////////
+    // memory map + fifos for the host control/status
+    ////////////////////////////////////////////////////////////////////
+
+    wire do_cmd = (state == STATE_ASSERT_DO_CMD);
+    wire do_sts = (state == STATE_ASSERT_DO_STS);
+
+    assign cmd_tvalid = do_cmd && cmd_tvalid_i[which_stream];
+    assign sts_tready = do_sts && sts_tready_i[which_stream];
+
+    genvar i;
+    generate
+    for (i=0; i < NUM_STREAMS; i=i+1) begin : stream_circuit
+
+        wire [PAGE_WIDTH-3:0] set_addr32 = set_addr[PAGE_WIDTH-1:2];
+        wire write_clear = set_stb && (set_addr32 == (0 + i*8));
+        wire write_addr  = set_stb && (set_addr32 == (1 + i*8));
+        wire write_size  = set_stb && (set_addr32 == (2 + i*8));
+        wire write_sts_rdy  = set_stb && (set_addr32 == (3 + i*8));
+        wire write_sts      = set_stb && (set_addr32 == (4 + i*8));
+
+        wire [PAGE_WIDTH-3:0] rb_addr32 = rb_addr[PAGE_WIDTH-1:2];
+        wire read_sig            = (rb_addr32 == (0 + i*8));
+        wire read_status         = (rb_addr32 == (4 + i*8));
+        wire read_sts_occupied   = (rb_addr32 == (5 + i*8));
+        wire read_cmd_addr_space = (rb_addr32 == (6 + i*8));
+        wire read_cmd_size_space = (rb_addr32 == (7 + i*8));
+
+        wire [15:0] sts_occupied, cmd_addr_space, cmd_size_space;
+        wire [7:0] sts_readback;
+
+        wire [15:0] this_stream = i;
+        always @* begin
+            if (read_sig) rb_data_i[i] <= {16'hACE0, this_stream};
+            else if (read_status) rb_data_i[i] <= {24'b0, sts_readback};
+            else if (read_sts_occupied) rb_data_i[i] <= {16'b0, sts_occupied};
+            else if (read_cmd_addr_space) rb_data_i[i] <= {16'b0, cmd_addr_space};
+            else if (read_cmd_size_space) rb_data_i[i] <= {16'b0, cmd_size_space};
+            else rb_data_i[i] <= 32'h12345678;
+        end
+
+        wire [31:0] cmd_addr, cmd_size;
+        wire cmd_addr_tvalid, cmd_size_tvalid;
+        assign cmd_data_i[i][32+39:32+36] = 4'b0; //reserved - 0?
+        assign cmd_data_i[i][32+35:64] = i[3:0]; //tag
+        assign cmd_data_i[i][63:32] = cmd_addr;
+        assign cmd_data_i[i][31] = 1'b0; //DRE ReAlignment Request
+        assign cmd_data_i[i][30] = 1'b1; //always EOF for tlast stream
+        assign cmd_data_i[i][29:24] = 6'b0; //DRE Stream Alignment
+        assign cmd_data_i[i][23] = 1'b1; // Transfer type, 0 = No addr incr / FIFO mode, 1 = incr addr
+        assign cmd_data_i[i][22:0] = cmd_size[22:0];
+
+        axi_fifo #(.WIDTH(32), .SIZE(CMDFIFO_DEPTH)) crl_addr_fifo
+        (
+            .clk(clk), .reset(rst), .clear(write_clear),
+            .i_tdata(set_data), .i_tvalid(write_addr), .i_tready(), .space(cmd_addr_space),
+            .o_tdata(cmd_addr), .o_tvalid(cmd_addr_tvalid), .o_tready(cmd_tready && do_cmd && (which_stream == i)), .occupied()
+        );
+
+        axi_fifo #(.WIDTH(32), .SIZE(CMDFIFO_DEPTH)) crl_size_fifo
+        (
+            .clk(clk), .reset(rst), .clear(write_clear),
+            .i_tdata(set_data), .i_tvalid(write_size), .i_tready(), .space(cmd_size_space),
+            .o_tdata(cmd_size), .o_tvalid(cmd_size_tvalid), .o_tready(cmd_tready && do_cmd && (which_stream == i)), .occupied()
+        );
+
+        assign cmd_tvalid_i[i] = cmd_addr_tvalid && cmd_size_tvalid && stream_valid;
+
+        wire dm_sts_tvalid = sts_tvalid && do_sts && (which_stream == i);
+
+        axi_fifo #(.WIDTH(8), .SIZE(CMDFIFO_DEPTH)) sts_fifo
+        (
+            .clk(clk), .reset(rst), .clear(),
+            .i_tdata((write_sts)?set_data[7:0]:sts_tdata), .i_tvalid(dm_sts_tvalid || write_sts), .i_tready(sts_tready_i[i]), .space(),
+            .o_tdata(sts_readback), .o_tvalid(), .o_tready(write_sts_rdy), .occupied(sts_occupied)
+        );
+
+    end
+    endgenerate
+
+    assign debug[1:0] = state;
+    assign debug[4] = cmd_tvalid;
+    assign debug[5] = cmd_tready;
+    assign debug[6] = sts_tvalid;
+    assign debug[7] = sts_tready;
+    assign debug[8] = stream_sel;
+    assign debug[9] = which_stream;
+    assign debug[15] = rb_addr[STREAMS_WIDTH+4:5];
+
+endmodule //zf_arbiter