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| author | Wade Fife <wade.fife@ettus.com> | 2020-08-24 21:29:28 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2020-08-28 15:02:41 -0500 |
| commit | 00f683c91486647f1711eb4c0b0a917078d29652 (patch) | |
| tree | e8a67a76d93acedf531a8268aa480941b63e290a /fpga/usrp3/lib/xge/tbench/verilog | |
| parent | c68977cffadf47d072e1c90903d5aee9a39541f9 (diff) | |
| download | uhd-00f683c91486647f1711eb4c0b0a917078d29652.tar.gz uhd-00f683c91486647f1711eb4c0b0a917078d29652.tar.bz2 uhd-00f683c91486647f1711eb4c0b0a917078d29652.zip | |
fpga: lib: Fix lint warnings
Fixes various synthesis/simulation warnings that were being generated
due to incorrectly sized constants.
Diffstat (limited to 'fpga/usrp3/lib/xge/tbench/verilog')
0 files changed, 0 insertions, 0 deletions