Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

1 files changed, 143 insertions, 0 deletions

diff --git a/fpga/usrp3/lib/xge/rtl/verilog/tx_checker.v b/fpga/usrp3/lib/xge/rtl/verilog/tx_checker.v
new file mode 100644
index 000000000..002746186
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/tx_checker.v
@@ -0,0 +1,143 @@
+//
+// Synthesizable Tx checker for 10G Ethernet MAC.
+// Generates deterministic packets that can be looped back and
+// checked for correctness
+//
+`define IDLE 0
+`define MAC1 1
+`define MAC2 2
+`define PAYLOAD1 3
+`define WAIT 4
+`define DONE 5
+
+
+module tx_checker
+  (
+   input clk156,
+   input rst,
+   input enable,
+   output reg done,
+   //
+   output reg pkt_tx_val,
+   output reg pkt_tx_sop,
+   output reg pkt_tx_eop,
+   output reg [2:0] pkt_tx_mod,
+   output reg [63:0] pkt_tx_data
+   );
+   
+   reg [10:0] 	 payload;
+   reg [10:0] 	 count;
+   reg [7:0] 	 state;
+   reg [9:0] 	 delay;
+   
+   
+   
+
+
+always @(posedge clk156)
+  if (rst)
+    begin
+       state <= `IDLE;
+       count <= 0;
+       payload <= 45; // 1 less than ethernet minimum payload size.\
+       done <= 0;
+       delay <= 0;
+       pkt_tx_val <= 0;
+       pkt_tx_sop <= 0;
+       pkt_tx_eop <= 0;
+       pkt_tx_data <= 0;
+       pkt_tx_mod <= 0;
+    end
+  else 
+    begin
+       state <= state;
+       pkt_tx_val <= 0;
+       pkt_tx_sop <= 0;
+       pkt_tx_eop <= 0;
+       pkt_tx_data <= 0;
+       pkt_tx_mod <= 0;
+       payload <= payload;
+       count <= count;
+       done <= 0;
+       delay <= delay;
+       
+       
+  
+       case(state)
+	 // Wait in IDLE state until enabled.
+	 // As we leave the idle state increment the payload count
+	 // so that we have a test pattern that changes each iteration.
+	 `IDLE: begin
+	    if (enable)
+	      begin
+		 if (payload == 1500)
+		   state <= `DONE;
+		 else
+		   begin
+		      payload <= payload + 1; // Might need to tweak this later..
+		      state <= `MAC1;
+		   end
+	      end
+	 end
+	 // Assert SOP (Start of Packet) for 1 cycle.
+	 // Assert VAL (Tx Valid) for duration of packet.
+	 // Put first 8 octets out, including
+	 // DST MAC addr and first 2 bytes of SRC MAC.
+	 `MAC1: begin
+	    pkt_tx_val <= 1;
+	    pkt_tx_sop <= 1;
+	    pkt_tx_data[63:16] <= 48'h0001020304; // DST MAC
+	    pkt_tx_data[15:0] <= 16'h0000; // SRC MAC msb's
+	    pkt_tx_mod <= 3'h0; // All octects valid
+	    state <= `MAC2;
+	 end
+	 // SOP now deasserted for rest of packet.
+	 // VAL remains asserted.
+	 // Tx rest of SRC MAC and ether type then first two data octets.
+	 `MAC2: begin
+	    pkt_tx_val <= 1;
+	    pkt_tx_data[63:32] <= 32'h05060708; // SRC MAC lsb's
+	    pkt_tx_data[31:16] <= 16'h88b5;     // Ethertype
+	    pkt_tx_data[15:0] <= 16'hBEEF;      // First 2 bytes of payload.
+	    pkt_tx_mod <= 3'h0; // All octects valid
+	    count <= payload - 2; // Preload counter for this packet
+	    state <= `PAYLOAD1;
+	 end
+	 // Iterate in this state until end of packet.
+	 // The first clock cycle in this state, SRC MAC and ETHERTYPE are being Tx'ed due to pipelining
+	 `PAYLOAD1: begin
+	    pkt_tx_val <= 1;
+	    pkt_tx_data <= {8{count[10:3]}}; // Data pattern is 64bit word count value.
+	    count <= count - 8;
+	    if ((count[10:3] == 0) || (count[10:0] == 8)) // down to 8 or less octects to Tx.
+	      begin
+		 pkt_tx_mod <= count[2:0];
+		 pkt_tx_eop <= 1;
+		 state <= `WAIT;
+		 delay <= 20; // 20 cycle delay in END state before Tx next packet
+	      end
+	 end // case: `PAYLOAD1
+	 // Because of pipelining EOP is actually asserted in this state
+	 // but we are already commited to the end of packet so no decisions need to be made.
+	 // Make signals idle ready for next state after.
+	 // Delay start of next packet to rate control test.
+	 `WAIT:begin
+	    delay <= delay - 1;
+	    if (delay == 0)
+	      state <= `IDLE;	    
+	 end
+	 // Have now transmitted one packet of every legal size (no jumbo frames)
+	 // Stay in this state asserting done flag until reset.
+	 `DONE:begin 	   
+	    state <= `DONE;
+	    done <= 1;
+	 end
+	 
+       endcase // case(state)
+      
+    end	    
+	    
+endmodule // tx_checker
+
+   
+   
\ No newline at end of file