Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

1 files changed, 275 insertions, 0 deletions

diff --git a/fpga/usrp3/lib/xge/rtl/verilog/rx_checker.v b/fpga/usrp3/lib/xge/rtl/verilog/rx_checker.v
new file mode 100644
index 000000000..cb775a8d8
--- /dev/null
+++ b/fpga/usrp3/lib/xge/rtl/verilog/rx_checker.v
@@ -0,0 +1,275 @@
+//
+// Synthesizable Rx checker for 10G Ethernet MAC.
+// Collects recevied packets and checks them against the deterministic expected result
+// to verify correct loopback functionality if used with the tx_checker.
+//
+
+`define IDLE 0
+`define SEARCH 1
+`define RECEIVE1 2
+`define RECEIVE2 3
+`define RECEIVE3 4
+`define DONE 5
+`define ERROR1 6
+`define ERROR2 7
+`define ERROR3 8
+
+
+module rx_checker
+  (
+   input clk156,
+   input rst,
+   input enable,
+   output reg done,
+   output reg correct,
+   output reg [1:0] error,
+   //
+   input pkt_rx_avail,
+   input pkt_rx_val,
+   input pkt_rx_sop,
+   input pkt_rx_eop,
+   input [2:0] pkt_rx_mod,
+   input [63:0] pkt_rx_data,
+   input pkt_rx_err,
+   output reg pkt_rx_ren
+   );
+
+
+   reg [10:0] 	 payload;
+   reg [10:0] 	 count;
+   reg [7:0] 	 state;
+
+   
+always @(posedge clk156)
+  if (rst)
+    begin
+       // Reset
+       state <= `IDLE;
+       done <= 0;
+       correct <= 0;
+       error <= 0;
+       pkt_rx_ren <= 0;
+       count <= 0;
+       payload <= 45; // 1 less than ethernet minimum payload size.\
+    end
+  else
+    begin
+       // Defaults
+       state <= state;
+       done <= 0;
+       correct <= 0;
+       error <= 0;
+       pkt_rx_ren <= 0;
+       count <= count;
+       payload <= payload;
+       
+            
+       case(state)
+	 // Wait in IDLE state until enabled.
+	 // incomming packets will not be detected in this state.
+	 `IDLE: begin
+	    if (enable)  
+	      state <= `SEARCH;
+	 end // case: `IDLE
+	 //
+	 // Search for pkt_rx_avail going asserted to show that a packet is in the MAC's FIFO's.
+	 // Then assert pkt_rx_ren back to MAC to start transfer. pkt_rx_ren now remains asserted until 
+	 // at least EOP, longer if pkt_rx_avail is still asserted at EOP as back-to-back Rx is possible.
+	 // We can come into this state with pkt_rx_ren already enabled for back-to-back Rx cases.
+	 //
+	 `SEARCH: begin
+	      if (pkt_rx_val)
+	      state <= `ERROR1;  // Illegal signalling
+	    else if (payload == 1500)
+	      state <= `DONE;
+	    else if (pkt_rx_avail)
+	      begin // rx_avail has been asserted, now assert rx_ren to start transfer.
+		 payload <= payload + 1; 
+		 pkt_rx_ren <= 1;
+		 state <= `RECEIVE1;
+	      end
+	 end
+	 //
+	 // Now wait for pkt_rx_val and pkt_rx_sop to assert in the same cycle with the first 
+	 // 8 octects of a new packet. When asserted check all data bits against expected data.
+	 // Go to error states if something doesn't match or work correctly.
+	 //
+	 `RECEIVE1: begin
+	    pkt_rx_ren <= 1;
+	    
+	    if (pkt_rx_err)
+	      state <= `ERROR3; // CRC error from MAC
+	    else if (pkt_rx_val && pkt_rx_sop && ~pkt_rx_eop)
+	      begin
+		 if ((pkt_rx_data[63:16] == 48'h0001020304) && (pkt_rx_data[15:0] == 16'h0000) && (pkt_rx_mod == 3'h0))
+		   state <= `RECEIVE2;
+		 else
+		   state <= `ERROR2; // Data missmatch error	 
+	      end	    
+	    else if (pkt_rx_val || pkt_rx_sop || pkt_rx_eop) // Error condition
+	      begin
+		 state <= `ERROR1; // Illegal signalling
+	      end
+	 end // case: `RECEIVE1
+	 //
+	 // Check all data bits against expected data.
+	 // Go to error states if something doesn't match or work correctly.
+	 //
+	 `RECEIVE2: begin
+	    pkt_rx_ren <= 1;
+	    
+	    if (pkt_rx_err)
+	      state <= `ERROR3; // CRC error from MAC
+	    else if (pkt_rx_val && ~pkt_rx_sop && ~pkt_rx_eop)
+	      begin
+		 if ((pkt_rx_data[63:32] == 32'h05060708) && 
+		     (pkt_rx_data[31:16] == 16'h88b5) && 
+		     (pkt_rx_data[15:0] == 16'hBEEF) && 
+		     (pkt_rx_mod == 3'h0))
+		   begin
+		      count <= payload - 2; // Preload counter for this packet
+		      state <= `RECEIVE3;
+		   end
+		 else
+		   state <= `ERROR2; // Data missmatch error	 
+	      end	    
+	    else if (~pkt_rx_val || pkt_rx_sop || pkt_rx_eop) // Error condition
+	      begin
+		 state <= `ERROR1; // Illegal signalling
+	      end
+	 end // case: `RECEIVE2
+	 //
+	 // Should now have received both MAC addresses, the ETHERTYPE and first 2 octects of payload.
+	 // Check remaining payload whilst looking for end of packet.
+	 // Currently don;pt support chained RX of packets, pkt_rx_en will go to 0.
+	 // (Remember packets are bigendian)
+	 //
+	 `RECEIVE3: begin
+	    count <= count - 8;
+	    
+	    if (pkt_rx_err)
+	      state <= `ERROR3; // CRC error from MAC
+	    else if (pkt_rx_val && ~pkt_rx_sop) 
+	      begin
+		 case({pkt_rx_eop,pkt_rx_mod})
+		   4'b0000: begin
+		      if (pkt_rx_data[63:0] == {8{count[10:3]}})
+			begin
+			   pkt_rx_ren <= 1;
+			   state <= `RECEIVE3;
+			end
+		      else
+			state <= `ERROR2; // Data missmatch error	 
+		   end
+		   4'b1000: begin
+		      if (pkt_rx_data[63:0] == {8{count[10:3]}})
+			begin
+			   pkt_rx_ren <= 0;	     
+			   state <= `SEARCH;
+			end
+		      else
+			state <= `ERROR2; // Data missmatch error	 
+		   end
+		   4'b1001: begin
+		      if (pkt_rx_data[63:56] == {1{count[10:3]}})	      
+			begin
+			   pkt_rx_ren <= 0;	     
+			   state <= `SEARCH;
+			end	     
+		      else
+			state <= `ERROR2; // Data missmatch error	 
+		   end
+		   4'b1010: begin
+		      if (pkt_rx_data[63:48] == {2{count[10:3]}})		
+			begin
+			   pkt_rx_ren <= 0;	     
+			   state <= `SEARCH;
+			end
+		      else
+			state <= `ERROR2; // Data missmatch error	 
+		   end
+		   4'b1011: begin
+		      if (pkt_rx_data[63:40] == {3{count[10:3]}})		
+			begin
+			   pkt_rx_ren <= 0;	     
+			   state <= `SEARCH;
+			end
+		      else
+			state <= `ERROR2; // Data missmatch error	 
+		   end
+		   4'b1100: begin
+		      if (pkt_rx_data[63:32] == {4{count[10:3]}})
+			begin
+			   pkt_rx_ren <= 0;	     
+			   state <= `SEARCH;
+			end
+		      else
+			state <= `ERROR2; // Data missmatch error	 
+		   end
+		   4'b1101: begin
+		      if (pkt_rx_data[63:24] == {5{count[10:3]}})
+			begin
+			   pkt_rx_ren <= 0;	     
+			   state <= `SEARCH;
+			end
+		      else
+			state <= `ERROR2; // Data missmatch error	 
+		   end
+		   4'b1110: begin
+		      if (pkt_rx_data[63:16] == {6{count[10:3]}})
+			begin
+			   pkt_rx_ren <= 0;	     
+			   state <= `SEARCH;
+			end
+		      else
+			state <= `ERROR2; // Data missmatch error	 
+		   end
+		   4'b1111: begin
+		      if (pkt_rx_data[63:8] == {7{count[10:3]}})
+			begin
+			   pkt_rx_ren <= 0;	     
+			   state <= `SEARCH;
+			end
+		      else
+			state <= `ERROR2; // Data missmatch error	 
+		   end
+		   default: state <= `ERROR1;  // Illegal signalling
+		 endcase // case({pkt_rx_eop,pkt_rx_mod})		 
+	      end	   
+	 end
+	 //
+	 // Finished. Received and verified full sequence. Now assert corret signal and done.
+	 // Stay in this state until reset.
+	 //
+	 `DONE: begin
+	    done <= 1;
+	    correct <= 1;
+	 end
+	 //
+	 // Signal protocol error.
+	 // Stay in this state until reset.
+	 //
+	 `ERROR1: begin
+	    done <= 1;
+	    error <= 1;
+	 end
+	 //
+	 // Data payload of packet did not match reference
+	 // Stay in this state until reset.
+	 //
+	 `ERROR2: begin
+	    done <= 1;
+	    error <= 2;
+	 end
+	 //
+	 // CRC error reported by MAC
+	 // Stay in this state until reset.
+	 //
+	 `ERROR3: begin
+	    done <= 1;
+	    error <= 3;
+	 end
+       endcase
+    end
+
+endmodule // rx_checker