Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

1 files changed, 266 insertions, 0 deletions

diff --git a/fpga/usrp3/lib/wishbone/axi_stream_to_wb.v b/fpga/usrp3/lib/wishbone/axi_stream_to_wb.v
new file mode 100644
index 000000000..6add3635a
--- /dev/null
+++ b/fpga/usrp3/lib/wishbone/axi_stream_to_wb.v
@@ -0,0 +1,266 @@
+//
+// Copyright 2012 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+
+// AXI stream to/from wishbone
+// Input is an axi stream which wites into a BRAM.
+// Output is an axi stream which reads from a BRAM.
+// This RAM can also be accessed from a wishbone interface.
+
+// From the wishbone interface we need to be able to:
+
+// Ask the module if a completed packet is available.
+// Read number of bytes/lines in the BRAM.
+// Release the completed packet.
+
+// Ask the module if an outgoing slot is available.
+// Write number of bytes/lines in the BRAM.
+// Release the completed packet.
+
+module axi_stream_to_wb
+#(
+    parameter AWIDTH = 13, //WB addr width and buffering size in bytes
+    parameter UWIDTH = 4, //stream user width
+    parameter CTRL_ADDR = 0 //ctrl/status register
+)
+(
+    //-- the wishbone interface
+    input clk_i, input rst_i,
+    input we_i, input stb_i, input cyc_i, output reg ack_o,
+    input [AWIDTH-1:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
+
+    //-- the axi stream interface input
+    input [63:0] rx_tdata,
+    input [3:0] rx_tuser,
+    input rx_tlast,
+    input rx_tvalid,
+    output rx_tready,
+
+    //-- the axi stream interface output
+    output [63:0] tx_tdata,
+    output [3:0] tx_tuser,
+    output tx_tlast,
+    output tx_tvalid,
+    input tx_tready,
+
+    output [31:0] debug_rx,
+    output [31:0] debug_tx
+);
+
+    reg stb_i_del;
+    always @(posedge clk_i) begin
+        if (rst_i) stb_i_del <= 0;
+        else stb_i_del <= stb_i;
+    end
+
+    reg ack_o_del;
+    always @(posedge clk_i) begin
+        if (rst_i)  ack_o_del <= 0;
+        else        ack_o_del <= ack_o;
+    end
+
+    //drive the ack signal
+    always @(posedge clk_i) begin
+        if (rst_i)      ack_o <= 0;
+        else if (we_i)  ack_o <= stb_i & ~ack_o;
+        else            ack_o <= stb_i & stb_i_del & ~ack_o & ~ack_o_del;
+    end
+
+    //control registers, status
+    reg [AWIDTH-1:0] tx_bytes, rx_bytes;
+    reg tx_error, rx_error;
+    wire rx_state_flag, tx_state_flag;
+    reg rx_proc_flag, tx_proc_flag;
+
+    //assign status
+    wire [31:0] status;
+    assign status[31] = rx_state_flag;
+    assign status[30] = tx_state_flag;
+    assign status[29] = rx_error;
+    assign status[AWIDTH-1:0] = rx_bytes;
+
+   // Create some piplining to break timing paths.
+   reg 		ctrl_addressed;
+   always @(posedge clk_i)
+     if (rst_i)
+       ctrl_addressed <= 1'b0;
+     else if(adr_i == CTRL_ADDR)
+       ctrl_addressed <= 1'b1;
+     else
+       ctrl_addressed <= 1'b0;
+       
+    //assign control
+    always @(posedge clk_i) begin
+        if (rst_i) begin
+            rx_proc_flag <= 0;
+            tx_proc_flag <= 0;
+            tx_error <= 0;
+            tx_bytes <= 0;
+        end
+        else if (we_i && ack_o && ctrl_addressed) begin
+            rx_proc_flag <= dat_i[31];
+            tx_proc_flag <= dat_i[30];
+            tx_error <= dat_i[29];
+            tx_bytes <= dat_i[AWIDTH-1:0];
+        end
+    end
+
+    //------------------------------------------------------------------
+    //-- block ram interface between wb and input stream
+    //------------------------------------------------------------------
+    reg [AWIDTH-4:0] rx_counter;
+    wire [63:0] rx_bram_data64;
+    ram_2port #(.DWIDTH(64), .AWIDTH(AWIDTH-3)) input_stream_bram
+    (
+        .clka(clk_i), .ena(rx_tready), .wea(rx_tvalid),
+        .addra(rx_counter), .dia(rx_tdata), .doa(),
+        .clkb(clk_i), .enb(stb_i), .web(1'b0),
+        .addrb(adr_i[AWIDTH-1:3]), .dib({64{1'b1}}), .dob(rx_bram_data64)
+    );
+
+    //select the data source, status, or upper/lower 32 from bram
+    wire [31:0] dat_o_pipeline;
+    assign dat_o_pipeline = ctrl_addressed ? status : ((!adr_i[2])? rx_bram_data64[63:32]: rx_bram_data64[31:0]);
+    always @(posedge clk_i) begin
+        dat_o <= dat_o_pipeline;
+    end
+
+    //------------------------------------------------------------------
+    //-- block ram interface between wb and output stream
+    //------------------------------------------------------------------
+    reg [AWIDTH-4:0] tx_counter;
+    wire enb_out;
+    wire [63:0] tx_bram_data64;
+    ram_2port #(.DWIDTH(64), .AWIDTH(AWIDTH-3)) output_stream_bram
+    (
+        .clka(clk_i), .ena(enb_out), .wea(1'b0),
+        .addra(tx_counter), .dia({64{1'b1}}), .doa(tx_tdata),
+        .clkb(clk_i), .enb(stb_i), .web(we_i && adr_i[2]),
+        .addrb(adr_i[AWIDTH-1:3]), .dib(tx_bram_data64), .dob()
+    );
+
+    //write 64 bit chunks, so register the lower write
+    reg [31:0] dat_i_reg;
+    always @(posedge clk_i) begin
+        if (we_i && stb_i && !adr_i[2]) dat_i_reg <= dat_i;
+    end
+    assign tx_bram_data64 = {dat_i_reg, dat_i};
+
+    //------------------------------------------------------------------
+    //-- state machine to drive input stream
+    //------------------------------------------------------------------
+    localparam RX_STATE_READY = 0; //waits for proc flag 0
+    localparam RX_STATE_WRITE = 1; //writes stream to bram
+    localparam RX_STATE_RELEASE = 2; //waits for proc to flag 1
+    reg [1:0] rx_state;
+
+    always @(posedge clk_i) begin
+        if (rst_i) begin
+            rx_state <= RX_STATE_READY;
+            rx_counter <= 0;
+            rx_error <= 0;
+            rx_bytes <= 0;
+        end
+        else case (rx_state)
+
+        RX_STATE_READY: begin
+            if (!rx_proc_flag) rx_state <= RX_STATE_WRITE;
+            rx_counter <= 0;
+        end
+
+        RX_STATE_WRITE: begin
+            if (rx_tready && rx_tvalid) begin
+                rx_counter <= rx_counter + 1'b1;
+                if (rx_tlast) begin
+                    rx_state <= RX_STATE_RELEASE;
+                    rx_bytes <= {rx_counter + 1'b1, rx_tuser[2:0]};
+                    rx_error <= rx_tuser[3];
+                end
+            end
+        end
+
+        RX_STATE_RELEASE: begin
+            if (rx_proc_flag) rx_state <= RX_STATE_READY;
+            rx_counter <= 0;
+        end
+
+        default: rx_state <= RX_STATE_READY;
+        endcase //rx_state
+    end
+
+    //flag tells the processor when it can grab some input buffer
+    assign rx_state_flag = (rx_state == RX_STATE_RELEASE);
+
+    //always ready to accept input data in the write state
+    assign rx_tready = (rx_state == RX_STATE_WRITE);
+
+    //------------------------------------------------------------------
+    //-- state machine to drive output stream
+    //------------------------------------------------------------------
+    localparam TX_STATE_READY = 0;  //waits for proc flag 0
+    localparam TX_STATE_WRITE = 1; //writes bram to stream
+    localparam TX_STATE_RELEASE = 2; //waits for proc to flag 1
+    reg [1:0] tx_state;
+
+    always @(posedge clk_i) begin
+        if (rst_i) begin
+            tx_state <= TX_STATE_READY;
+            tx_counter <= 0;
+        end
+        else case (tx_state)
+
+        TX_STATE_READY: begin
+            if (tx_proc_flag) begin
+                tx_state <= TX_STATE_WRITE;
+                tx_counter <= 1;
+            end
+            else tx_counter <= 0;
+        end
+
+        TX_STATE_WRITE: begin
+            if (tx_tready && tx_tvalid) begin
+                tx_counter <= tx_counter + 1'b1;
+                if (tx_tlast) begin
+                    tx_state <= TX_STATE_RELEASE;
+                end
+            end
+        end
+
+        TX_STATE_RELEASE: begin
+            if (!tx_proc_flag) tx_state <= TX_STATE_READY;
+            tx_counter <= 0;
+        end
+
+        default: tx_state <= TX_STATE_READY;
+        endcase //tx_state
+    end
+
+    //flag tells the processor when it can grab available out buffer
+    assign tx_state_flag = (tx_state == TX_STATE_READY);
+
+    //the output user bus assignment (non-zero only at end)
+    assign tx_tuser = (tx_tlast)? {tx_error, tx_bytes[2:0]} : 4'b0;
+
+    //end of frame signal
+    assign tx_tlast = (tx_counter == tx_bytes[AWIDTH-1:3]);
+
+    //output is always valid in state write
+    assign tx_tvalid = (tx_state == TX_STATE_WRITE);
+
+    //enable the read so we can pre-read due to read 1 cycle delay
+    assign enb_out = (tx_state == TX_STATE_WRITE)? (tx_tvalid && tx_tready) : 1'b1;
+
+    assign debug_rx = {
+        rx_state, rx_tlast, rx_tvalid, rx_tready, rx_tuser[2:0], //8
+        rx_proc_flag, rx_state_flag, rx_tdata[21:0] //24
+    };
+    assign debug_tx = {
+        tx_state, tx_tlast, tx_tvalid, tx_tready, tx_tuser[2:0], //8
+        tx_proc_flag, tx_state_flag, tx_tdata[21:0] //24
+    };
+
+endmodule //axi_stream_to_wb