Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

1 files changed, 272 insertions, 0 deletions

diff --git a/fpga/usrp3/lib/vivado_ipi/axi_dmac/up_axi.v b/fpga/usrp3/lib/vivado_ipi/axi_dmac/up_axi.v
new file mode 100644
index 000000000..db62e659a
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/axi_dmac/up_axi.v
@@ -0,0 +1,272 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module up_axi (
+
+  // reset and clocks
+
+  up_rstn,
+  up_clk,
+
+  // axi4 interface
+
+  up_axi_awvalid,
+  up_axi_awaddr,
+  up_axi_awready,
+  up_axi_wvalid,
+  up_axi_wdata,
+  up_axi_wstrb,
+  up_axi_wready,
+  up_axi_bvalid,
+  up_axi_bresp,
+  up_axi_bready,
+  up_axi_arvalid,
+  up_axi_araddr,
+  up_axi_arready,
+  up_axi_rvalid,
+  up_axi_rresp,
+  up_axi_rdata,
+  up_axi_rready,
+
+  // pcore interface
+
+  up_wreq,
+  up_waddr,
+  up_wdata,
+  up_wack,
+  up_rreq,
+  up_raddr,
+  up_rdata,
+  up_rack);
+
+  // parameters
+
+  parameter   ADDRESS_WIDTH = 14;
+  localparam  AW = ADDRESS_WIDTH - 1;
+
+  // reset and clocks
+
+  input           up_rstn;
+  input           up_clk;
+
+  // axi4 interface
+
+  input           up_axi_awvalid;
+  input   [31:0]  up_axi_awaddr;
+  output          up_axi_awready;
+  input           up_axi_wvalid;
+  input   [31:0]  up_axi_wdata;
+  input   [ 3:0]  up_axi_wstrb;
+  output          up_axi_wready;
+  output          up_axi_bvalid;
+  output  [ 1:0]  up_axi_bresp;
+  input           up_axi_bready;
+  input           up_axi_arvalid;
+  input   [31:0]  up_axi_araddr;
+  output          up_axi_arready;
+  output          up_axi_rvalid;
+  output  [ 1:0]  up_axi_rresp;
+  output  [31:0]  up_axi_rdata;
+  input           up_axi_rready;
+
+  // pcore interface
+
+  output          up_wreq;
+  output  [AW:0]  up_waddr;
+  output  [31:0]  up_wdata;
+  input           up_wack;
+  output          up_rreq;
+  output  [AW:0]  up_raddr;
+  input   [31:0]  up_rdata;
+  input           up_rack;
+
+  // internal registers
+
+  reg             up_axi_awready = 'd0;
+  reg             up_axi_wready = 'd0;
+  reg             up_axi_bvalid = 'd0;
+  reg             up_wack_d = 'd0;
+  reg             up_wsel = 'd0;
+  reg             up_wreq = 'd0;
+  reg     [AW:0]  up_waddr = 'd0;
+  reg     [31:0]  up_wdata = 'd0;
+  reg     [ 4:0]  up_wcount = 'd0;
+  reg             up_axi_arready = 'd0;
+  reg             up_axi_rvalid = 'd0;
+  reg     [31:0]  up_axi_rdata = 'd0;
+  reg             up_rack_d = 'd0;
+  reg     [31:0]  up_rdata_d = 'd0;
+  reg             up_rsel = 'd0;
+  reg             up_rreq = 'd0;
+  reg     [AW:0]  up_raddr = 'd0;
+  reg     [ 4:0]  up_rcount = 'd0;
+
+  // internal signals
+
+  wire            up_wack_s;
+  wire            up_rack_s;
+  wire    [31:0]  up_rdata_s;
+
+  // write channel interface
+
+  assign up_axi_bresp = 2'd0;
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 1'b0) begin
+      up_axi_awready <= 'd0;
+      up_axi_wready <= 'd0;
+      up_axi_bvalid <= 'd0;
+    end else begin
+      if (up_axi_awready == 1'b1) begin
+        up_axi_awready <= 1'b0;
+      end else if (up_wack_s == 1'b1) begin
+        up_axi_awready <= 1'b1;
+      end
+      if (up_axi_wready == 1'b1) begin
+        up_axi_wready <= 1'b0;
+      end else if (up_wack_s == 1'b1) begin
+        up_axi_wready <= 1'b1;
+      end
+      if ((up_axi_bready == 1'b1) && (up_axi_bvalid == 1'b1)) begin
+        up_axi_bvalid <= 1'b0;
+      end else if (up_wack_d == 1'b1) begin
+        up_axi_bvalid <= 1'b1;
+      end
+    end
+  end
+
+  assign up_wack_s = (up_wcount == 5'h1f) ? 1'b1 : (up_wcount[4] & up_wack);
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 1'b0) begin
+      up_wack_d <= 'd0;
+      up_wsel <= 'd0;
+      up_wreq <= 'd0;
+      up_waddr <= 'd0;
+      up_wdata <= 'd0;
+      up_wcount <= 'd0;
+    end else begin
+      up_wack_d <= up_wack_s;
+      if (up_wsel == 1'b1) begin
+        if ((up_axi_bready == 1'b1) && (up_axi_bvalid == 1'b1)) begin
+          up_wsel <= 1'b0;
+        end
+        up_wreq <= 1'b0;
+        up_waddr <= up_waddr;
+        up_wdata <= up_wdata;
+      end else begin
+        up_wsel <= up_axi_awvalid & up_axi_wvalid;
+        up_wreq <= up_axi_awvalid & up_axi_wvalid;
+        up_waddr <= up_axi_awaddr[AW+2:2];
+        up_wdata <= up_axi_wdata;
+      end
+      if (up_wack_s == 1'b1) begin
+        up_wcount <= 5'h00;
+      end else if (up_wcount[4] == 1'b1) begin
+        up_wcount <= up_wcount + 1'b1;
+      end else if (up_wreq == 1'b1) begin
+        up_wcount <= 5'h10;
+      end
+    end
+  end
+
+  // read channel interface
+
+  assign up_axi_rresp = 2'd0;
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 1'b0) begin
+      up_axi_arready <= 'd0;
+      up_axi_rvalid <= 'd0;
+      up_axi_rdata <= 'd0;
+    end else begin
+      if (up_axi_arready == 1'b1) begin
+        up_axi_arready <= 1'b0;
+      end else if (up_rack_s == 1'b1) begin
+        up_axi_arready <= 1'b1;
+      end
+      if ((up_axi_rready == 1'b1) && (up_axi_rvalid == 1'b1)) begin
+        up_axi_rvalid <= 1'b0;
+        up_axi_rdata <= 32'd0;
+      end else if (up_rack_d == 1'b1) begin
+        up_axi_rvalid <= 1'b1;
+        up_axi_rdata <= up_rdata_d;
+      end
+    end
+  end
+
+  assign up_rack_s = (up_rcount == 5'h1f) ? 1'b1 : (up_rcount[4] & up_rack);
+  assign up_rdata_s = (up_rcount == 5'h1f) ? {2{16'hdead}} : up_rdata;
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (up_rstn == 1'b0) begin
+      up_rack_d <= 'd0;
+      up_rdata_d <= 'd0;
+      up_rsel <= 'd0;
+      up_rreq <= 'd0;
+      up_raddr <= 'd0;
+      up_rcount <= 'd0;
+    end else begin
+      up_rack_d <= up_rack_s;
+      up_rdata_d <= up_rdata_s;
+      if (up_rsel == 1'b1) begin
+        if ((up_axi_rready == 1'b1) && (up_axi_rvalid == 1'b1)) begin
+          up_rsel <= 1'b0;
+        end
+        up_rreq <= 1'b0;
+        up_raddr <= up_raddr;
+      end else begin
+        up_rsel <= up_axi_arvalid;
+        up_rreq <= up_axi_arvalid;
+        up_raddr <= up_axi_araddr[AW+2:2];
+      end
+      if (up_rack_s == 1'b1) begin
+        up_rcount <= 5'h00;
+      end else if (up_rcount[4] == 1'b1) begin
+        up_rcount <= up_rcount + 1'b1;
+      end else if (up_rreq == 1'b1) begin
+        up_rcount <= 5'h10;
+      end
+    end
+  end
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************