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| author | michael-west <michael.west@ettus.com> | 2014-04-08 17:46:53 -0700 |
|---|---|---|
| committer | michael-west <michael.west@ettus.com> | 2014-04-08 17:46:53 -0700 |
| commit | 0624dcc37c4bb428c7858da2b60cf10aa5b03e47 (patch) | |
| tree | c8b9f2887939ee452eadb782f9a42106bc3acbf7 /fpga/usrp3/lib/vita/chdr_8sc_to_16sc.hex | |
| parent | 47bf17b50a305228cfd07ff6fbaff3ac4a30e811 (diff) | |
| download | uhd-0624dcc37c4bb428c7858da2b60cf10aa5b03e47.tar.gz uhd-0624dcc37c4bb428c7858da2b60cf10aa5b03e47.tar.bz2 uhd-0624dcc37c4bb428c7858da2b60cf10aa5b03e47.zip | |
Fix for BUG #403: Visible frequency drift on Finite Rx with N210 & SBX
- Added initialization of clock and time sources
Diffstat (limited to 'fpga/usrp3/lib/vita/chdr_8sc_to_16sc.hex')
0 files changed, 0 insertions, 0 deletions