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author | Ben Hilburn <ben.hilburn@ettus.com> | 2014-07-25 09:28:19 -0700 |
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committer | Ben Hilburn <ben.hilburn@ettus.com> | 2014-07-25 09:28:19 -0700 |
commit | 9b4def474fae59717f60c18d11f909a02a178d6f (patch) | |
tree | d59eda6fad7ad4666b6e864d3884287051c8cef4 /fpga/usrp3/lib/timing/pps.v | |
parent | 42b47cea158d3a767a87ff4da71a00b3243e14f1 (diff) | |
parent | 83e07d3dc70a9254fd1dcafcd7597d2fa1892550 (diff) | |
download | uhd-9b4def474fae59717f60c18d11f909a02a178d6f.tar.gz uhd-9b4def474fae59717f60c18d11f909a02a178d6f.tar.bz2 uhd-9b4def474fae59717f60c18d11f909a02a178d6f.zip |
Merge 'maint' into x300/bug513
Diffstat (limited to 'fpga/usrp3/lib/timing/pps.v')
-rw-r--r-- | fpga/usrp3/lib/timing/pps.v | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/timing/pps.v b/fpga/usrp3/lib/timing/pps.v new file mode 100644 index 000000000..49d3641b7 --- /dev/null +++ b/fpga/usrp3/lib/timing/pps.v @@ -0,0 +1,22 @@ +// +// Copyright 2014 Ettus Research LLC +// + +module pps_generator + #(parameter CLK_FREQ=0, DUTY=25) + (input clk, input reset, output pps); + + reg[31:0] count; + + always @(posedge clk) begin + if (reset) begin + count <= 32'b1; + end else if (count >= CLK_FREQ) begin + count <= 32'b1; + end else begin + count <= count + 1'b1; + end + end + + assign pps = (count < CLK_FREQ * DUTY / 100); +endmodule //pps_generator |