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| author | Ashish Chaudhari <ashish@ettus.com> | 2014-09-24 18:45:31 -0700 |
|---|---|---|
| committer | Ashish Chaudhari <ashish@ettus.com> | 2014-09-24 18:45:31 -0700 |
| commit | 64d71dcbc5fa6790385b288de25224d386b047b0 (patch) | |
| tree | 05d1048d44f5347f39b4036163a758e0a75d1ea3 /fpga/usrp3/lib/packet_proc/Makefile.srcs | |
| parent | ecdd34c08b79117c4f739b336daeb4b9d2bc8df3 (diff) | |
| download | uhd-64d71dcbc5fa6790385b288de25224d386b047b0.tar.gz uhd-64d71dcbc5fa6790385b288de25224d386b047b0.tar.bz2 uhd-64d71dcbc5fa6790385b288de25224d386b047b0.zip | |
fpga: Multiple X300 FPGA bugfixes and enhancements
- Fixed 10GigE firmware communication issues and sequence errors for TX
- Multiple changes to help ease timing closure
- Cleaned up build scripts
- Switched to Xilinx ISE 14.7 as the default build tool for X300
Diffstat (limited to 'fpga/usrp3/lib/packet_proc/Makefile.srcs')
| -rw-r--r-- | fpga/usrp3/lib/packet_proc/Makefile.srcs | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/packet_proc/Makefile.srcs b/fpga/usrp3/lib/packet_proc/Makefile.srcs index 078609514..c4bf877a0 100644 --- a/fpga/usrp3/lib/packet_proc/Makefile.srcs +++ b/fpga/usrp3/lib/packet_proc/Makefile.srcs @@ -18,4 +18,6 @@ cvita_insert_tlast.v \ cvita_dest_lookup.v \ cvita_chunker.v \ cvita_dechunker.v \ +axis_packet_debug.v \ +cvita_packet_debug.v \ )) |