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| author | Ben Hilburn <ben.hilburn@ettus.com> | 2014-02-14 12:05:07 -0800 |
|---|---|---|
| committer | Ben Hilburn <ben.hilburn@ettus.com> | 2014-02-14 12:05:07 -0800 |
| commit | ff1546f8137f7f92bb250f685561b0c34cc0e053 (patch) | |
| tree | 7fa6fd05c8828df256a1b20e2935bd3ba9899e2c /fpga/usrp3/lib/io_port2/LvFpga_Chinch_Interface.v | |
| parent | 4f691d88123784c2b405816925f1a1aef69d18c1 (diff) | |
| download | uhd-ff1546f8137f7f92bb250f685561b0c34cc0e053.tar.gz uhd-ff1546f8137f7f92bb250f685561b0c34cc0e053.tar.bz2 uhd-ff1546f8137f7f92bb250f685561b0c34cc0e053.zip | |
Pushing the bulk of UHD-3.7.0 code.
Diffstat (limited to 'fpga/usrp3/lib/io_port2/LvFpga_Chinch_Interface.v')
| -rw-r--r-- | fpga/usrp3/lib/io_port2/LvFpga_Chinch_Interface.v | 81 |
1 files changed, 81 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/io_port2/LvFpga_Chinch_Interface.v b/fpga/usrp3/lib/io_port2/LvFpga_Chinch_Interface.v new file mode 100644 index 000000000..253773967 --- /dev/null +++ b/fpga/usrp3/lib/io_port2/LvFpga_Chinch_Interface.v @@ -0,0 +1,81 @@ +/*
+-------------------------------------------------------------------------------
+--
+-- File: LvFpga_Chinch_Interface.vhd
+-- Author: Ashish Chaudhari
+-- Original Project: EttusUsrpB250Top
+-- Date: 1 Oct 2013
+--
+-------------------------------------------------------------------------------
+-- (c) 2013 Copyright National Instruments Corporation
+-- All Rights Reserved
+-- National Instruments Internal Information
+-------------------------------------------------------------------------------
+*/
+
+`include "LvFpga_Chinch_Interface.vh"
+
+module LvFpga_Chinch_Interface
+(
+ input aIoResetIn_n,
+ output bBusReset,
+
+ input BusClk,
+ input Rio40Clk,
+ input IDelayRefClk,
+ input aRioClkPllLocked,
+ output aRioClkPllReset,
+
+ output aIoReadyOut,
+ input aIoReadyIn,
+ output aIoPort2Restart,
+
+ input IoRxClock,
+ input IoRxClock_n,
+ input [`LVFPGA_IFACE_LINK_WIDTH-1:0] irIoRxData,
+ input [`LVFPGA_IFACE_LINK_WIDTH-1:0] irIoRxData_n,
+ input irIoRxHeader,
+ input irIoRxHeader_n,
+
+ output IoTxClock,
+ output IoTxClock_n,
+ output [`LVFPGA_IFACE_LINK_WIDTH-1:0] itIoTxData,
+ output [`LVFPGA_IFACE_LINK_WIDTH-1:0] itIoTxData_n,
+ output itIoTxHeader,
+ output itIoTxHeader_n,
+
+ input [(`LVFPGA_IFACE_NUM_RX_DMA_CNT*`LVFPGA_IFACE_DMA_CHAN_WIDTH)-1:0] bDmaRxData,
+ input [`LVFPGA_IFACE_NUM_RX_DMA_CNT-1:0] bDmaRxValid,
+ output [`LVFPGA_IFACE_NUM_RX_DMA_CNT-1:0] bDmaRxReady,
+ output [`LVFPGA_IFACE_NUM_RX_DMA_CNT-1:0] bDmaRxEnabled,
+ output [(`LVFPGA_IFACE_NUM_RX_DMA_CNT*`LVFPGA_IFACE_DMA_SIZE_WIDTH)-1:0] bDmaRxFifoFreeCnt,
+
+ output [(`LVFPGA_IFACE_NUM_TX_DMA_CNT*`LVFPGA_IFACE_DMA_CHAN_WIDTH)-1:0] bDmaTxData,
+ output [`LVFPGA_IFACE_NUM_TX_DMA_CNT-1:0] bDmaTxValid,
+ input [`LVFPGA_IFACE_NUM_TX_DMA_CNT-1:0] bDmaTxReady,
+ output [`LVFPGA_IFACE_NUM_TX_DMA_CNT-1:0] bDmaTxEnabled,
+ output [(`LVFPGA_IFACE_NUM_TX_DMA_CNT*`LVFPGA_IFACE_DMA_SIZE_WIDTH)-1:0] bDmaTxFifoFullCnt,
+
+ output bUserRegPortInWt,
+ output bUserRegPortInRd,
+ output [`LVFPGA_IFACE_UREG_ADDR_WIDTH-1:0] bUserRegPortInAddr,
+ output [`LVFPGA_IFACE_UREG_DATA_WIDTH-1:0] bUserRegPortInData,
+ output [`LVFPGA_IFACE_UREG_SIZE_WIDTH-1:0] bUserRegPortInSize,
+ input [`LVFPGA_IFACE_UREG_DATA_WIDTH-1:0] bUserRegPortOutData,
+ input bUserRegPortOutDataValid,
+ input bUserRegPortOutReady,
+
+ input bChinchRegPortOutWt,
+ input bChinchRegPortOutRd,
+ input [`LVFPGA_IFACE_CREG_ADDR_WIDTH-1:0] bChinchRegPortOutAddr,
+ input [`LVFPGA_IFACE_CREG_DATA_WIDTH-1:0] bChinchRegPortOutData,
+ input [`LVFPGA_IFACE_CREG_SIZE_WIDTH-1:0] bChinchRegPortOutSize,
+ output [`LVFPGA_IFACE_CREG_DATA_WIDTH-1:0] bChinchRegPortInData,
+ output bChinchRegPortInDataValid,
+ output bChinchRegPortInReady,
+
+ output aIrq
+) /* synthesis syn_black_box syn_noprune=1 */;
+// This module serves as an API wrapper for LvFpga_Chinch_Interface.ngc and we don't want
+// the tool to accidentally prune out it contents. Hence the syn_black_box syn_noprune=1 directives.
+endmodule
|