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| author | michael-west <michael.west@ettus.com> | 2020-09-04 15:32:12 -0700 |
|---|---|---|
| committer | michael-west <michael.west@ettus.com> | 2020-09-04 15:45:51 -0700 |
| commit | 413ebee61254fd0b9ab0cd11b475b8a849579cd8 (patch) | |
| tree | d1807d3e38eb57cba61a71bb2661b422616cee71 /fpga/usrp3/lib/fifo_200 | |
| parent | be53058a47c6b2925103d44595f06fd6fb85e4be (diff) | |
| download | uhd-413ebee61254fd0b9ab0cd11b475b8a849579cd8.tar.gz uhd-413ebee61254fd0b9ab0cd11b475b8a849579cd8.tar.bz2 uhd-413ebee61254fd0b9ab0cd11b475b8a849579cd8.zip | |
E320: Revert addition of Replay block
The DMA FIFO is needed for DDR3 BIST, so it is being restored for now.
Signed-off-by: michael-west <michael.west@ettus.com>
Diffstat (limited to 'fpga/usrp3/lib/fifo_200')
0 files changed, 0 insertions, 0 deletions