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author | Ben Hilburn <ben.hilburn@ettus.com> | 2013-10-10 10:17:27 -0700 |
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committer | Ben Hilburn <ben.hilburn@ettus.com> | 2013-10-10 10:17:27 -0700 |
commit | 0df4b801a34697f2058b4a7b95e08d2a0576c9db (patch) | |
tree | be10e78d1a97c037a9e7492360a178d1873b9c09 /fpga/usrp3/lib/fifo/axi_fifo64_to_fifo32.v | |
parent | 6e7bc850b66e8188718248b76b729c7cf9c89700 (diff) | |
download | uhd-0df4b801a34697f2058b4a7b95e08d2a0576c9db.tar.gz uhd-0df4b801a34697f2058b4a7b95e08d2a0576c9db.tar.bz2 uhd-0df4b801a34697f2058b4a7b95e08d2a0576c9db.zip |
Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt Ettus.
Diffstat (limited to 'fpga/usrp3/lib/fifo/axi_fifo64_to_fifo32.v')
-rw-r--r-- | fpga/usrp3/lib/fifo/axi_fifo64_to_fifo32.v | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/fifo/axi_fifo64_to_fifo32.v b/fpga/usrp3/lib/fifo/axi_fifo64_to_fifo32.v new file mode 100644 index 000000000..46b021600 --- /dev/null +++ b/fpga/usrp3/lib/fifo/axi_fifo64_to_fifo32.v @@ -0,0 +1,31 @@ + +module axi_fifo64_to_fifo32 + (input clk, input reset, input clear, + input [63:0] i_tdata, input [2:0] i_tuser, input i_tlast, input i_tvalid, output i_tready, + output [31:0] o_tdata, output [1:0] o_tuser, output o_tlast, output o_tvalid, input o_tready + ); + + wire short_last = i_tlast & ((i_tuser == 3'd1) | (i_tuser == 3'd2) | (i_tuser == 3'd3) | (i_tuser == 3'd4)); + + reg state; + always @(posedge clk) + if(reset | clear) + state <= 1'b0; + else + if(i_tvalid & o_tready) + case(state) + 1'b0 : + if(~short_last) + state <= 1'b1; + 1'b1 : + state <= 1'b0; + endcase // case (state) + + assign o_tdata = (state == 0) ? i_tdata[63:32] : i_tdata[31:0]; + assign o_tuser = o_tlast ? i_tuser[1:0] : 2'd0; + assign o_tlast = i_tlast & ((state == 1'b1) | short_last); + + assign o_tvalid = i_tvalid; + assign i_tready = o_tready & ((state == 1'b1) | short_last); + +endmodule // axi_fifo64_to_fifo32 |