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authorMartin Braun <martin.braun@ettus.com>2014-10-07 11:25:20 +0200
committerMartin Braun <martin.braun@ettus.com>2014-10-07 11:25:20 +0200
commitfd3e84941de463fa1a7ebab0a69515b4bf2614cd (patch)
tree3fa721a13d41d2c0451d663a59a220a38fd5e614 /fpga/usrp3/lib/dsp/sign_extend.v
parent3b66804e41891e358c790b453a7a59ec7462dba4 (diff)
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Removed copy of FPGA source files.
Diffstat (limited to 'fpga/usrp3/lib/dsp/sign_extend.v')
-rw-r--r--fpga/usrp3/lib/dsp/sign_extend.v23
1 files changed, 0 insertions, 23 deletions
diff --git a/fpga/usrp3/lib/dsp/sign_extend.v b/fpga/usrp3/lib/dsp/sign_extend.v
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-// -*- verilog -*-
-//
-// USRP - Universal Software Radio Peripheral
-//
-// Copyright (C) 2003 Matt Ettus
-//
-
-//
-
-
-// Sign extension "macro"
-// bits_out should be greater than bits_in
-
-module sign_extend (in,out);
- parameter bits_in=0; // FIXME Quartus insists on a default
- parameter bits_out=0;
-
- input [bits_in-1:0] in;
- output [bits_out-1:0] out;
-
- assign out = {{(bits_out-bits_in){in[bits_in-1]}},in};
-
-endmodule