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authorBen Hilburn <ben.hilburn@ettus.com>2013-10-10 10:17:27 -0700
committerBen Hilburn <ben.hilburn@ettus.com>2013-10-10 10:17:27 -0700
commit0df4b801a34697f2058b4a7b95e08d2a0576c9db (patch)
treebe10e78d1a97c037a9e7492360a178d1873b9c09 /fpga/usrp3/lib/dsp/add2_and_clip_reg.v
parent6e7bc850b66e8188718248b76b729c7cf9c89700 (diff)
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Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt Ettus.
Diffstat (limited to 'fpga/usrp3/lib/dsp/add2_and_clip_reg.v')
-rw-r--r--fpga/usrp3/lib/dsp/add2_and_clip_reg.v25
1 files changed, 25 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/dsp/add2_and_clip_reg.v b/fpga/usrp3/lib/dsp/add2_and_clip_reg.v
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+++ b/fpga/usrp3/lib/dsp/add2_and_clip_reg.v
@@ -0,0 +1,25 @@
+
+module add2_and_clip_reg
+ #(parameter WIDTH=16)
+ (input clk,
+ input rst,
+ input [WIDTH-1:0] in1,
+ input [WIDTH-1:0] in2,
+ input strobe_in,
+ output reg [WIDTH-1:0] sum,
+ output reg strobe_out);
+
+ wire [WIDTH-1:0] sum_int;
+
+ add2_and_clip #(.WIDTH(WIDTH)) add2_and_clip (.in1(in1),.in2(in2),.sum(sum_int));
+
+ always @(posedge clk)
+ if(rst)
+ sum <= 0;
+ else if(strobe_in)
+ sum <= sum_int;
+
+ always @(posedge clk)
+ strobe_out <= strobe_in;
+
+endmodule // add2_and_clip_reg