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author | michael-west <michael.west@ettus.com> | 2014-03-25 15:59:03 -0700 |
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committer | michael-west <michael.west@ettus.com> | 2014-03-25 15:59:03 -0700 |
commit | 04292f9b109479b639add31f83fd240a6387f488 (patch) | |
tree | 4b8723a4ae63626029704f901ee0083bb23bc1e9 /fpga/usrp3/lib/control/serial_to_settings_tb.v | |
parent | 09915aa57bc88099cbcbbe925946ae65bc0ad8f0 (diff) | |
parent | ff8a1252f3a51369abe0a165d963b781089ec66c (diff) | |
download | uhd-04292f9b109479b639add31f83fd240a6387f488.tar.gz uhd-04292f9b109479b639add31f83fd240a6387f488.tar.bz2 uhd-04292f9b109479b639add31f83fd240a6387f488.zip |
Merge branch 'master' into mwest/b200_docs
Diffstat (limited to 'fpga/usrp3/lib/control/serial_to_settings_tb.v')
-rw-r--r-- | fpga/usrp3/lib/control/serial_to_settings_tb.v | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/control/serial_to_settings_tb.v b/fpga/usrp3/lib/control/serial_to_settings_tb.v index 8111c115e..adaa2c985 100644 --- a/fpga/usrp3/lib/control/serial_to_settings_tb.v +++ b/fpga/usrp3/lib/control/serial_to_settings_tb.v @@ -45,6 +45,34 @@ module serial_to_settings_tb(); .set_data(set_data) ); + // Nasty HAck to convert settings to wishbone crudely. + reg wb_stb; + wire wb_ack_o; + + + always @(posedge clk) + if (reset) + wb_stb <= 0; + else + wb_stb <= set_stb ? 1 : ((wb_ack_o) ? 0 : wb_stb); + + simple_uart debug_uart + ( + .clk_i(clk), + .rst_i(reset), + .we_i(wb_stb), + .stb_i(wb_stb), + .cyc_i(wb_stb), + .ack_o(wb_ack_o), + .adr_i(set_addr[2:0]), + .dat_i(set_data[31:0]), + .dat_o(), + .rx_int_o(), + .tx_int_o(), + .tx_o(txd), + .rx_i(rxd), + .baud_o() + ); // // Bring in a simulation script here |