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| author | Javier Valenzuela <javier.valenzuela@ni.com> | 2022-06-14 10:10:59 -0500 |
|---|---|---|
| committer | skooNI <60897865+skooNI@users.noreply.github.com> | 2022-07-20 15:57:20 -0500 |
| commit | 32786c63930bc532bca1f25ab8d3404b5773edfd (patch) | |
| tree | e7fc7fc4bfe01584575354d6d81b937ad7de553a /fpga/usrp3/lib/control/ram_2port.v | |
| parent | 802696d9eb7cd0487514fbce79c6bdaf90a4aadc (diff) | |
| download | uhd-32786c63930bc532bca1f25ab8d3404b5773edfd.tar.gz uhd-32786c63930bc532bca1f25ab8d3404b5773edfd.tar.bz2 uhd-32786c63930bc532bca1f25ab8d3404b5773edfd.zip | |
fpga: lib: Add read-only strategy for port B in 2-port RAM
Diffstat (limited to 'fpga/usrp3/lib/control/ram_2port.v')
| -rw-r--r-- | fpga/usrp3/lib/control/ram_2port.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp3/lib/control/ram_2port.v b/fpga/usrp3/lib/control/ram_2port.v index 96db90061..6f32409c1 100644 --- a/fpga/usrp3/lib/control/ram_2port.v +++ b/fpga/usrp3/lib/control/ram_2port.v @@ -54,7 +54,7 @@ module ram_2port #( parameter DWIDTH = 32, // Width of the memory block parameter AWIDTH = 9, // log2 of the depth of the memory block - parameter RW_MODE = "READ-FIRST", // Read-write mode {READ-FIRST, WRITE-FIRST, NO-CHANGE} + parameter RW_MODE = "READ-FIRST", // Read-write mode {READ-FIRST, WRITE-FIRST, NO-CHANGE, B-READ-ONLY} parameter RAM_TYPE = "AUTOMATIC", // Type of RAM to infer {AUTOMATIC, REG, LUTRAM, BRAM, URAM} parameter OUT_REG = 0, // Instantiate an output register? (+1 cycle of read latency) parameter INIT_FILE = "" // Optionally initialize memory with this file |