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| author | Martin Braun <martin.braun@ettus.com> | 2014-10-07 11:25:20 +0200 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2014-10-07 11:25:20 +0200 |
| commit | fd3e84941de463fa1a7ebab0a69515b4bf2614cd (patch) | |
| tree | 3fa721a13d41d2c0451d663a59a220a38fd5e614 /fpga/usrp3/lib/control/por_gen.v | |
| parent | 3b66804e41891e358c790b453a7a59ec7462dba4 (diff) | |
| download | uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.gz uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.bz2 uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.zip | |
Removed copy of FPGA source files.
Diffstat (limited to 'fpga/usrp3/lib/control/por_gen.v')
| -rw-r--r-- | fpga/usrp3/lib/control/por_gen.v | 25 |
1 files changed, 0 insertions, 25 deletions
diff --git a/fpga/usrp3/lib/control/por_gen.v b/fpga/usrp3/lib/control/por_gen.v deleted file mode 100644 index 0e4fcd88a..000000000 --- a/fpga/usrp3/lib/control/por_gen.v +++ /dev/null @@ -1,25 +0,0 @@ -// -// Copyright 2013 Ettus Research LLC -// - - - -module por_gen - (input clk, - output reset_out); - - reg por_rst; - reg [7:0] por_counter = 8'h0; - - always @(posedge clk) - if (por_counter != 8'h55) - begin - por_counter <= por_counter + 8'h1; - por_rst <= 1'b1; - end - else - por_rst <= 1'b0; - - assign reset_out = por_rst; - -endmodule // por_gen |