Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

1 files changed, 193 insertions, 0 deletions

diff --git a/fpga/usrp3/lib/axi/axi_fast_extract_tlast.v b/fpga/usrp3/lib/axi/axi_fast_extract_tlast.v
new file mode 100644
index 000000000..59e925caf
--- /dev/null
+++ b/fpga/usrp3/lib/axi/axi_fast_extract_tlast.v
@@ -0,0 +1,193 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+//
+// Ultra fast critical path FIFO.
+// Only 2 entrys but no combinatorial feed through paths
+//
+
+
+module axi_fast_extract_tlast
+  #(parameter WIDTH=64)
+  (
+   input clk,
+   input reset,
+   input clear,
+   //
+   input [WIDTH-1:0] i_tdata,
+   input i_tvalid,
+   output reg i_tready,
+   //
+   output [WIDTH-1:0] o_tdata,
+   output o_tlast,
+   output reg o_tvalid,
+   input  o_tready
+   );
+
+   reg [WIDTH:0] data_reg1, data_reg2;
+
+   reg [1:0] 	   fifo_state;
+   
+   localparam EMPTY = 0;
+   localparam HALF = 1;
+   localparam FULL = 2;
+
+   reg [1:0]  extract_state;
+   
+   localparam IDLE = 0;
+   localparam EXTRACT1 = 1;
+   localparam EXTRACT2 = 2;
+   localparam EXTRACT3 = 3;
+
+   
+   always @(posedge clk) 
+     if (reset | clear) begin
+	fifo_state <= EMPTY;
+     end else begin
+	case (fifo_state)
+	  // Nothing in either register.
+	  // Upstream can always push data to us.
+	  // Downstream has nothing to take from us.
+	  EMPTY: begin
+	     if ((extract_state == IDLE) && (i_tdata == 64'hDEADBEEFFEEDCAFE) && i_tvalid) begin
+		// Embeded escpae code received.
+		extract_state <= EXTRACT1;
+		i_tready <= 1'b1;
+		o_tvalid <= 1'b0;
+		fifo_state <= EMPTY;
+	     end else if ((extract_state == EXTRACT1) && i_tvalid) begin
+		// Now work out if its a genuine embeded tlast or emulation.
+		i_tready <= 1'b1;
+		o_tvalid <= 1'b0;
+		fifo_state <= EMPTY;
+		if (i_tdata[31:0] == 'h1) begin
+		   extract_state <= EXTRACT2;
+		end else begin
+		   extract_state <= EXTRACT3;
+		end
+	     end else if ((extract_state == EXTRACT2) && i_tvalid) begin
+		// Extract tlast.
+		data_reg1 <= {1'b1,i_tdata};
+		i_tready <= 1'b1;
+		o_tvalid <= 1'b1;
+		fifo_state <= HALF;
+		extract_state <= IDLE;
+	     end else if (i_tvalid) begin
+		// Get here both for normal data and for EXTRACT3 emulation data.
+		data_reg1 <= {1'b0,i_tdata};
+		fifo_state <= HALF;
+		extract_state <= IDLE;
+		i_tready <= 1'b1;
+		o_tvalid <= 1'b1;
+	     end else begin
+		// Nothing to do.
+		fifo_state <= EMPTY;
+		i_tready <= 1'b1;
+		o_tvalid <= 1'b0;
+	     end
+	  end
+	  // First Register Full.
+	  // Upstream can always push data to us.
+	  // Downstream can always read from us.
+	  HALF: begin
+	     if ((extract_state == IDLE) && (i_tdata == 64'hDEADBEEFFEEDCAFE) && i_tvalid) begin
+		// Embeded escpae code received.
+		extract_state <= EXTRACT1;
+		if (o_tready) begin
+		   // If meanwhile we get read then go empty...
+		   i_tready <= 1'b1;
+		   o_tvalid <= 1'b0;
+		   fifo_state <= EMPTY;
+		end else begin
+		   // ...else stay half full.
+		   fifo_state <= HALF;
+		   i_tready <= 1'b1;
+		   o_tvalid <= 1'b1;
+		end
+	     end else if ((extract_state == EXTRACT1) && i_tvalid) begin
+		// Now work out if its a genuine embeded tlast or emulation.
+		if (i_tdata[31:0] == 'h1) begin
+		   extract_state <= EXTRACT2;
+		end else begin
+		   extract_state <= EXTRACT3;
+		end
+		if (o_tready) begin
+		   // If meanwhile we get read then go empty...
+		   i_tready <= 1'b1;
+		   o_tvalid <= 1'b0;
+		   fifo_state <= EMPTY;
+		end else begin
+		   // ...else stay half full.
+		   fifo_state <= HALF;
+		   i_tready <= 1'b1;
+		   o_tvalid <= 1'b1;
+		end		
+	     end else if ((extract_state == EXTRACT2) && i_tvalid) begin
+		// Extract tlast.
+		data_reg1 <= {1'b1,i_tdata};
+		extract_state <= IDLE;
+		if (o_tready) begin
+		   // We get read and writen same cycle...
+		   i_tready <= 1'b1;
+		   o_tvalid <= 1'b1;
+		   fifo_state <= HALF;
+		end else begin
+		   // ...or we get written and go full.
+		   data_reg2 <= data_reg1;
+		   i_tready <= 1'b0;
+		   o_tvalid <= 1'b1;
+		   fifo_state <= FULL;
+		end	
+	     end else if (i_tvalid) begin
+		// Get here both for normal data and for EXTRACT3 emulation data.
+		data_reg1 <= {1'b0,i_tdata};
+		extract_state <= IDLE;
+		if (o_tready) begin
+		   // We get read and writen same cycle...
+		   fifo_state <= HALF;
+		   i_tready <= 1'b1;
+		   o_tvalid <= 1'b1;
+		end else begin
+		   // ...or we get written and go full.
+		   data_reg2 <= data_reg1;
+		   i_tready <= 1'b0;
+		   o_tvalid <= 1'b1;
+		   fifo_state <= FULL;
+		end	
+	     end else if (o_tready) begin // if (i_tvalid)
+		// Only getting read this cycle so go empty
+		fifo_state <= EMPTY;
+		i_tready <= 1'b1;
+		o_tvalid <= 1'b0;
+	     end else begin
+		// Absolutley nothing happens, everything stays the same.
+		fifo_state <= HALF;
+		i_tready <= 1'b1;
+		o_tvalid <= 1'b1;
+	     end
+	  end // case: HALF
+	  // Both Registers Full.
+	  // Upstream can not push to us in this fifo_state.
+	  // Downstream can always read from us.
+	  FULL: begin
+	     if (o_tready) begin
+		fifo_state <= HALF;
+		i_tready <= 1'b1;
+		o_tvalid <= 1'b1;
+	     end
+	     else begin
+		fifo_state <= FULL;
+		i_tready <= 1'b0;
+		o_tvalid <= 1'b1;
+	     end
+	  end
+	endcase // case(fifo_state)
+     end // else: !if(reset | clear)
+   
+   assign {o_tlast,o_tdata} = (fifo_state == FULL) ? data_reg2 : data_reg1;
+   
+
+endmodule // axi_fast_extract_tlast