Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

1 files changed, 147 insertions, 0 deletions

diff --git a/fpga/usrp3/lib/axi/axi_extract_tlast.v b/fpga/usrp3/lib/axi/axi_extract_tlast.v
new file mode 100644
index 000000000..9afef3c35
--- /dev/null
+++ b/fpga/usrp3/lib/axi/axi_extract_tlast.v
@@ -0,0 +1,147 @@
+//
+// Copyright 2014 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+//
+// AXI stream neds N+1 bits to transmit packets of N bits so that the LAST bit can be represented.
+// LAST occurs relatively infrequently and can be synthesized by using an in-band ESC code to generate
+// a multi-word sequence to encode it (and the escape character when it appears as data input).
+//
+// 0x1234567887654321 with last becomes
+// 0xDEADBEEFFEEDCAFE 0x0000000000000001 0x1234567887654321
+//
+// 0xDEADBEEFFEEDCAFE with last becomes
+// 0xDEADBEEFFEEDCAFE 0x0000000000000001 0xDEADBEEFFEEDCAFE
+//
+// 0xDEADBEEFFEEDCAFE without last becomes
+// 0xDEADBEEFFEEDCAFE 0x0000000000000000 0xDEADBEEFFEEDCAFE
+//
+
+module axi_extract_tlast #(
+  parameter WIDTH=64,
+  parameter VALIDATE_CHECKSUM=0
+) (
+   input clk,
+   input reset,
+   input clear,
+   //
+   input [WIDTH-1:0] i_tdata,
+   input i_tvalid,
+   output reg i_tready,
+   //
+   output [WIDTH-1:0] o_tdata,
+   output reg o_tlast,
+   output reg o_tvalid,
+   input  o_tready,
+   //
+   output reg checksum_error
+);
+
+   reg [1:0] state, next_state;
+   
+   localparam IDLE = 0;
+   localparam EXTRACT1 = 1;
+   localparam EXTRACT2 = 2;
+   localparam EXTRACT3 = 3;
+   
+   assign     o_tdata = i_tdata;
+
+   reg        checksum_error_pre;
+   reg [31:0] checksum, old_checksum;
+
+   always @(posedge clk) 
+      if (reset | clear) begin
+         checksum <= 0;
+         old_checksum <= 0;
+      end else if (VALIDATE_CHECKSUM && o_tready && i_tvalid && o_tlast) begin
+         checksum <= 0;
+         old_checksum <= 0;
+      end else if (VALIDATE_CHECKSUM && i_tready && i_tvalid && (state == IDLE)) begin
+         checksum <= checksum ^ i_tdata[31:0] ^ i_tdata[63:32];
+         old_checksum <= checksum;
+      end
+
+   always @(posedge clk)
+      checksum_error <= checksum_error_pre;
+
+   always @(posedge clk) 
+      if (reset | clear) begin
+         state <= IDLE;
+      end else begin
+         state <= next_state;
+      end 
+
+   always @(*) begin
+      checksum_error_pre = 0;
+      case(state)
+         //
+         // Search for Escape sequence "0xDEADBEEFFEEDCAFE"
+         // If ESC found don't pass data downstream but transition to next state.
+         // else pass data downstream.
+         //
+         IDLE: begin
+            o_tlast = 1'b0;
+            if ((i_tdata == 64'hDEADBEEFFEEDCAFE) && i_tvalid) begin
+               next_state = EXTRACT1;
+               o_tvalid = 1'b0;
+               i_tready = 1'b1;
+            end else begin
+               next_state = IDLE;
+               o_tvalid = i_tvalid;
+               i_tready = o_tready;
+            end // else: !if((i_tdata == 'hDEADBEEFFEEDCAFE) && i_tvalid)
+         end // case: IDLE
+         //
+         // Look at next data. If it's a 0x1 then o_tlast should be asserted with next data word.
+         // if it's 0x0 then it signals emulation of the Escape code in the original data stream
+         // and we should just pass the next data word through unchanged with no o_tlast indication.
+         //
+         EXTRACT1: begin
+            o_tvalid = 1'b0;
+            i_tready = 1'b1;
+            o_tlast = 1'b0;
+            if (i_tvalid) begin
+               if (i_tdata[31:0] == 'h1) begin
+                  if (VALIDATE_CHECKSUM && (old_checksum != i_tdata[63:32])) 
+                     checksum_error_pre = 1'b1;
+                  next_state = EXTRACT2;
+               end else  begin
+                  // We assume emulation and don't look for illegal codes.
+                  next_state = EXTRACT3;
+               end // else: !if(i_tdata == 'h1)
+            end else begin // if (i_tvalid)
+               next_state = EXTRACT1;
+            end // else: !if(i_tvalid)
+         end // case: EXTRACT1
+         //
+         // Assert o_tlast with data word.
+         //
+         EXTRACT2: begin
+            o_tvalid = i_tvalid;
+            i_tready = o_tready;
+            o_tlast = 1'b1;
+            if (i_tvalid & o_tready)
+               next_state = IDLE;
+            else
+               next_state = EXTRACT2;
+         end
+         //
+         // Emulation, don't assert o_tlast with dataword.
+         //
+         EXTRACT3: begin
+            o_tvalid = i_tvalid;
+            i_tready = o_tready;
+            o_tlast = 1'b0;
+            if (i_tvalid & o_tready)
+               next_state = IDLE;
+            else
+               next_state = EXTRACT2;
+         end
+      endcase // case(state)
+   end
+
+endmodule // axi_extract_tlast
+
+  
\ No newline at end of file