Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

1 files changed, 152 insertions, 0 deletions

diff --git a/fpga/usrp3/lib/axi/axi_embed_tlast_tkeep.v b/fpga/usrp3/lib/axi/axi_embed_tlast_tkeep.v
new file mode 100644
index 000000000..4adb91fa6
--- /dev/null
+++ b/fpga/usrp3/lib/axi/axi_embed_tlast_tkeep.v
@@ -0,0 +1,152 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Brand
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axi_embed_tlast_tkeep
+//
+// Description:
+//
+//   This module takes the TLAST and TKEEP values of an AXI-Stream interface
+//   and embeds them into the data stream. This allows a data pipe to be used
+//   that isn't wide enough for the TDATA, TLAST,and TKEEP to be passed through
+//   in parallel. Since TLAST and TKEEP are only usually needed for one word
+//   per packet, this also reduces the amount of memory required to store a
+//   packet. Note that this module only supports TKEEP at the end of a packet
+//   when TLAST is asserted. See also axi_extract_tlast_tkeep.
+//
+//   This embedding is accomplished by using an escape sequence using the word
+//   0xDEADBEEF as the escape code. If TLAST and TKEEP are both 0 (the usual
+//   case) then no escape sequence is used. Any word that has "DEADBEEF" in the
+//   most significant position is considered an escape word. The least
+//   significant bits of the escape word contain the TKEEP and TLAST bits. The
+//   word following the escape word is the normal data word associated with
+//   those TLAST and TKEEP values.
+//
+//   Here are some examples for the case where DATA_W = 64
+//
+//     0x1234567887654321 with TLAST=0 and TKEEP=0 becomes
+//     0x1234567887654321
+//
+//     0x1234567887654321 with TLAST=1 and TKEEP=0 becomes
+//     0xDEADBEEF00000001 0x1234567887654321
+//
+//     0x1234567887654321 with TLAST=1 and TKEEP=2 becomes
+//     0xDEADBEEF00000005 0x1234567887654321
+//
+//     0x1234567887654321 with TLAST=0 and TKEEP=1 becomes
+//     0x1234567887654321 (because TKEEP is ignored when TLAST=0)
+//
+//     0xDEADBEEFFEEDCAFE without TLAST=0 and TKEEP=0 becomes
+//     0xDEADBEEF00000000 0xDEADBEEFFEEDCAFE
+//
+//     0xDEADBEEFFEEDCAFE with TLAST=0 and TKEEP=1 becomes
+//     0xDEADBEEF00000002 0xDEADBEEFFEEDCAFE
+//
+
+module axi_embed_tlast_tkeep #(
+  parameter DATA_W = 64,
+  parameter KEEP_W = DATA_W/8
+) (
+  input clk,
+  input rst,
+
+  // Input AXI-Stream
+  input  [DATA_W-1:0] i_tdata,
+  input  [KEEP_W-1:0] i_tkeep,
+  input               i_tlast,
+  input               i_tvalid,
+  output              i_tready,
+
+  // Output AXI-Stream
+  output reg [DATA_W-1:0] o_tdata,
+  output                  o_tvalid,
+  input                   o_tready
+);
+
+  localparam                  ESC_WORD_W = 32;
+  localparam [ESC_WORD_W-1:0] ESC_WORD   = 'hDEADBEEF;
+
+
+  //---------------------------------------------------------------------------
+  // Parameter Checking
+  //---------------------------------------------------------------------------
+
+  if (DATA_W < ESC_WORD_W+KEEP_W+1) begin : gen_assertion
+    // Cause an error if DATA_W is not large enough.
+    DATA_W_is_not_large_enough_to_store_escape_code_TKEEP_and_TLAST();
+  end
+
+
+  //---------------------------------------------------------------------------
+  // State Machine
+  //---------------------------------------------------------------------------
+
+  localparam PASS   = 0;
+  localparam ESCAPE = 1;
+
+  localparam ST_IDLE = 0;
+  localparam ST_DATA = 1;
+
+  reg [0:0] state = ST_IDLE;
+  reg [0:0] next_state;
+
+  reg [0:0] select;
+
+  always @(posedge clk) begin
+    if (rst) begin
+      state <= ST_IDLE;
+    end else begin if (o_tready)
+      state <= next_state;
+    end
+  end
+
+  always @(*) begin
+    case(state)
+      ST_IDLE: begin
+        if (i_tlast && i_tvalid) begin
+          next_state = ST_DATA;
+          select     = ESCAPE;
+        end else if ((i_tdata[DATA_W-1 -: ESC_WORD_W] == ESC_WORD) && i_tvalid) begin
+          next_state = ST_DATA;
+          select     = ESCAPE;
+        end else begin
+          next_state = ST_IDLE;
+          select     = PASS;
+        end
+      end
+
+      ST_DATA: begin
+        select = PASS;
+        if (i_tvalid) begin
+          next_state = ST_IDLE;
+        end else begin
+          next_state = ST_DATA;
+        end
+      end
+    endcase
+  end
+
+
+  //---------------------------------------------------------------------------
+  // Output Multiplexers
+  //---------------------------------------------------------------------------
+
+  always @(*) begin
+    case(select)
+      PASS   : begin
+        o_tdata = i_tdata;
+      end
+      ESCAPE : begin
+        o_tdata                         = {DATA_W{1'b0}};
+        o_tdata[DATA_W-1 -: ESC_WORD_W] = ESC_WORD;
+        o_tdata[       1 +:     KEEP_W] = i_tkeep;
+        o_tdata[       0 +:          1] = i_tlast;
+      end
+    endcase
+  end
+
+  assign o_tvalid = (select == PASS) ? i_tvalid : 1'b1;
+  assign i_tready = (select == PASS) ? o_tready : 1'b0;
+
+endmodule