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authorJosh Blum <josh@joshknows.com>2010-12-13 16:47:48 -0800
committerJosh Blum <josh@joshknows.com>2010-12-13 16:47:48 -0800
commitfd0c2dc1c53240afed5eba9e73a4b090cdcdf78a (patch)
tree30e15ab4e2bde2175a9373234f634db9e7738d3d /fpga/usrp2/top/u2plus/u2plus_core.v
parente436016638b4d2b81d50ee2de98c271615eee806 (diff)
parentc97440838aa740fc335c59914f6dfd6f492b69f8 (diff)
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Merge branch 'fpga_ise12'
Diffstat (limited to 'fpga/usrp2/top/u2plus/u2plus_core.v')
-rw-r--r--fpga/usrp2/top/u2plus/u2plus_core.v7
1 files changed, 4 insertions, 3 deletions
diff --git a/fpga/usrp2/top/u2plus/u2plus_core.v b/fpga/usrp2/top/u2plus/u2plus_core.v
index 8426826e2..4e0b190ef 100644
--- a/fpga/usrp2/top/u2plus/u2plus_core.v
+++ b/fpga/usrp2/top/u2plus/u2plus_core.v
@@ -16,8 +16,8 @@ module u2plus_core
output [1:0] debug_clk,
// Expansion
- input exp_pps_in,
- output exp_pps_out,
+ input exp_time_in,
+ output exp_time_out,
// GMII
// GMII-CTRL
@@ -683,7 +683,8 @@ module u2plus_core
time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit
(.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
- .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int));
+ .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int),
+ .exp_time_in(exp_time_in), .exp_time_out(exp_time_out));
// /////////////////////////////////////////////////////////////////////////////////////////
// Debug Pins