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author | Josh Blum <josh@joshknows.com> | 2010-04-15 11:24:41 -0700 |
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committer | Josh Blum <josh@joshknows.com> | 2010-04-15 11:24:41 -0700 |
commit | 3a196c5d614fbec9b1010b3082245614ba5e0dc9 (patch) | |
tree | 784f075298f5d86c9e7429ce0ff977deaf4315c8 /fpga/usrp2/timing/time_compare.v | |
parent | cbf7a0916f0455743d8446a8edc0f0775e3e63ed (diff) | |
parent | 05d77f772317de5d925301aa11bb9a880656dd05 (diff) | |
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Merge branch 'udp'
Diffstat (limited to 'fpga/usrp2/timing/time_compare.v')
-rw-r--r-- | fpga/usrp2/timing/time_compare.v | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/fpga/usrp2/timing/time_compare.v b/fpga/usrp2/timing/time_compare.v new file mode 100644 index 000000000..a21c9f8e0 --- /dev/null +++ b/fpga/usrp2/timing/time_compare.v @@ -0,0 +1,23 @@ + +// Top 32 bits are integer seconds, bottom 32 are clock ticks within a second + +module time_compare + (input [63:0] time_now, + input [63:0] trigger_time, + output now, + output early, + output late, + output too_early); + + wire sec_match = (time_now[63:32] == trigger_time[63:32]); + wire sec_late = (time_now[63:32] > trigger_time[63:32]); + + wire tick_match = (time_now[31:0] == trigger_time[31:0]); + wire tick_late = (time_now[31:0] > trigger_time[31:0]); + + assign now = sec_match & tick_match; + assign late = sec_late | (sec_match & tick_late); + assign early = ~now & ~late; + assign too_early = (trigger_time[63:32] > (time_now[63:32] + 4)); // Don't wait too long + +endmodule // time_compare |