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author | Josh Blum <josh@joshknows.com> | 2011-11-07 17:09:07 -0800 |
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committer | Josh Blum <josh@joshknows.com> | 2011-11-07 17:09:07 -0800 |
commit | 11f1390bbde65c60f45962acb128cac1ce21e474 (patch) | |
tree | 372f2e426781de9885889bec6aa98697006268ec /fpga/usrp2/sdr_lib/round.v | |
parent | 902818f50bbd486138a7d4cd2ce9ba3661f4a732 (diff) | |
parent | bcb80c5cf9a2117f9d6d22b8e793ea2ecb68ed1f (diff) | |
download | uhd-11f1390bbde65c60f45962acb128cac1ce21e474.tar.gz uhd-11f1390bbde65c60f45962acb128cac1ce21e474.tar.bz2 uhd-11f1390bbde65c60f45962acb128cac1ce21e474.zip |
Merge branch 'fpga_master' into uhd_next
Diffstat (limited to 'fpga/usrp2/sdr_lib/round.v')
-rw-r--r-- | fpga/usrp2/sdr_lib/round.v | 30 |
1 files changed, 27 insertions, 3 deletions
diff --git a/fpga/usrp2/sdr_lib/round.v b/fpga/usrp2/sdr_lib/round.v index 7a137d702..26d5a4cf4 100644 --- a/fpga/usrp2/sdr_lib/round.v +++ b/fpga/usrp2/sdr_lib/round.v @@ -2,7 +2,7 @@ // // USRP - Universal Software Radio Peripheral // -// Copyright (C) 2007 Matt Ettus +// Copyright (C) 2011 Matt Ettus // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -24,12 +24,36 @@ module round #(parameter bits_in=0, - parameter bits_out=0) + parameter bits_out=0, + parameter round_to_zero=0, // original behavior + parameter round_to_nearest=1, // lowest noise + parameter trunc=0) // round to negative infinity (input [bits_in-1:0] in, output [bits_out-1:0] out, output [bits_in-bits_out:0] err); - assign out = in[bits_in-1:bits_in-bits_out] + (in[bits_in-1] & |in[bits_in-bits_out-1:0]); + wire round_corr,round_corr_trunc,round_corr_rtz,round_corr_nearest,round_corr_nearest_safe; + + assign round_corr_trunc = 0; + assign round_corr_rtz = (in[bits_in-1] & |in[bits_in-bits_out-1:0]); + assign round_corr_nearest = in[bits_in-bits_out-1]; + + generate + if(bits_in-bits_out > 1) + assign round_corr_nearest_safe = (~in[bits_in-1] & (&in[bits_in-2:bits_out])) ? 0 : + round_corr_nearest; + else + assign round_corr_nearest_safe = round_corr_nearest; + endgenerate + + + assign round_corr = round_to_nearest ? round_corr_nearest_safe : + trunc ? round_corr_trunc : + round_to_zero ? round_corr_rtz : + 0; // default to trunc + + assign out = in[bits_in-1:bits_in-bits_out] + round_corr; + assign err = in - {out,{(bits_in-bits_out){1'b0}}}; endmodule // round |