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| author | Josh Blum <josh@joshknows.com> | 2012-01-05 12:34:53 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-01-05 12:34:53 -0800 |
| commit | 1c76adac7a5f4caa2ab07bc451b156980258130c (patch) | |
| tree | 589d4ca92c78046e7cb9c70a1b4e558d5665099f /fpga/usrp2/opencores/i2c/rtl/verilog | |
| parent | 4cb26d251df4d701c6154689c794abfe721567e5 (diff) | |
| download | uhd-1c76adac7a5f4caa2ab07bc451b156980258130c.tar.gz uhd-1c76adac7a5f4caa2ab07bc451b156980258130c.tar.bz2 uhd-1c76adac7a5f4caa2ab07bc451b156980258130c.zip | |
usrp1: initialize tick_rate prop (fixes readback)
Diffstat (limited to 'fpga/usrp2/opencores/i2c/rtl/verilog')
0 files changed, 0 insertions, 0 deletions