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| author | Josh Blum <josh@joshknows.com> | 2010-04-15 11:24:24 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-04-15 11:24:24 -0700 |
| commit | 05d77f772317de5d925301aa11bb9a880656dd05 (patch) | |
| tree | 0910bfb9265fab1644a3d3a1706719f1b038d193 /fpga/usrp2/opencores/i2c/CVS/Entries | |
| parent | 16818dc98e97b69a028c47e66ebfb16e32565533 (diff) | |
| download | uhd-05d77f772317de5d925301aa11bb9a880656dd05.tar.gz uhd-05d77f772317de5d925301aa11bb9a880656dd05.tar.bz2 uhd-05d77f772317de5d925301aa11bb9a880656dd05.zip | |
moved usrp1 and usrp2 fpga dirs into fpga subdirectory
Diffstat (limited to 'fpga/usrp2/opencores/i2c/CVS/Entries')
| -rw-r--r-- | fpga/usrp2/opencores/i2c/CVS/Entries | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/fpga/usrp2/opencores/i2c/CVS/Entries b/fpga/usrp2/opencores/i2c/CVS/Entries new file mode 100644 index 000000000..d6947544a --- /dev/null +++ b/fpga/usrp2/opencores/i2c/CVS/Entries @@ -0,0 +1,8 @@ +D/bench//// +D/doc//// +D/documentation//// +D/rtl//// +D/sim//// +D/software//// +D/verilog//// +D/vhdl//// |