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| author | Josh Blum <josh@joshknows.com> | 2010-11-23 13:36:42 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-11-23 13:36:42 -0800 |
| commit | bb0572a960edf54486a4be746c681adaac0fa398 (patch) | |
| tree | 7afb46e99eaf799a478fcde841eb78d7698e9c39 /fpga/usrp2/opencores/aemb/rtl | |
| parent | 8ce75a3ca7a51f4bdee87d78a610a0f2519473ae (diff) | |
| download | uhd-bb0572a960edf54486a4be746c681adaac0fa398.tar.gz uhd-bb0572a960edf54486a4be746c681adaac0fa398.tar.bz2 uhd-bb0572a960edf54486a4be746c681adaac0fa398.zip | |
fpga: performed a forceful checkout of fpga to overwrite with current fpga code
Diffstat (limited to 'fpga/usrp2/opencores/aemb/rtl')
| -rw-r--r-- | fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v index 38ca3a023..6c066d5d9 100644 --- a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v +++ b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v @@ -11,7 +11,7 @@ module aeMB_core_BE (input sys_clk_i, input sys_rst_i, // Instruction port - output [14:0] if_adr, + output [ISIZ-1:0] if_adr, input [31:0] if_dat, // Data port output dwb_we_o, @@ -34,7 +34,7 @@ module aeMB_core_BE assign dwb_cyc_o = dwb_stb_o; assign iwb_ack_i = 1'b1; - assign if_adr = iwb_adr_o[14:0]; + assign if_adr = iwb_adr_o[ISIZ-1:0]; assign iwb_dat_i = if_dat; // Note some "wishbone" instruction fetch signals pruned on external interface |