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| author | Josh Blum <josh@joshknows.com> | 2010-06-15 18:24:33 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-06-15 18:24:33 -0700 |
| commit | edcc2df10ba59ed91ac9513c2dc1d36e155caaec (patch) | |
| tree | 1a1ec2c0b5500990c991c27af03dbe48c10ce7ca /fpga/usrp2/opencores/Makefile.srcs | |
| parent | a89d684ba2b81c6e18d348965dffb919edb56fea (diff) | |
| parent | 9445315e6a5cdfb29c4ead73b0fcd4d5fd75b900 (diff) | |
| download | uhd-edcc2df10ba59ed91ac9513c2dc1d36e155caaec.tar.gz uhd-edcc2df10ba59ed91ac9513c2dc1d36e155caaec.tar.bz2 uhd-edcc2df10ba59ed91ac9513c2dc1d36e155caaec.zip | |
Merge branch 'master' of ettus.sourcerepo.com:ettus/fpga into uhd_master
Conflicts:
fpga/.gitignore
Diffstat (limited to 'fpga/usrp2/opencores/Makefile.srcs')
| -rw-r--r-- | fpga/usrp2/opencores/Makefile.srcs | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/fpga/usrp2/opencores/Makefile.srcs b/fpga/usrp2/opencores/Makefile.srcs new file mode 100644 index 000000000..30360a17d --- /dev/null +++ b/fpga/usrp2/opencores/Makefile.srcs @@ -0,0 +1,28 @@ +# +# Copyright 2010 Ettus Research LLC +# + +################################################## +# Open Cores Sources +################################################## +OPENCORES_SRCS = $(abspath $(addprefix $(BASE_DIR)/../opencores/, \ +8b10b/decode_8b10b.v \ +8b10b/encode_8b10b.v \ +aemb/rtl/verilog/aeMB_bpcu.v \ +aemb/rtl/verilog/aeMB_core_BE.v \ +aemb/rtl/verilog/aeMB_ctrl.v \ +aemb/rtl/verilog/aeMB_edk32.v \ +aemb/rtl/verilog/aeMB_ibuf.v \ +aemb/rtl/verilog/aeMB_regf.v \ +aemb/rtl/verilog/aeMB_xecu.v \ +i2c/rtl/verilog/i2c_master_bit_ctrl.v \ +i2c/rtl/verilog/i2c_master_byte_ctrl.v \ +i2c/rtl/verilog/i2c_master_defines.v \ +i2c/rtl/verilog/i2c_master_top.v \ +i2c/rtl/verilog/timescale.v \ +spi/rtl/verilog/spi_clgen.v \ +spi/rtl/verilog/spi_defines.v \ +spi/rtl/verilog/spi_shift.v \ +spi/rtl/verilog/spi_top.v \ +spi/rtl/verilog/timescale.v \ +)) |