Merge branch 'fpga_next' into next

5 files changed, 172 insertions, 43 deletions

diff --git a/fpga/usrp2/gpmc/Makefile.srcs b/fpga/usrp2/gpmc/Makefile.srcs
index bff6ae3e0..bf0c0ecfd 100644
--- a/fpga/usrp2/gpmc/Makefile.srcs
+++ b/fpga/usrp2/gpmc/Makefile.srcs
@@ -17,4 +17,6 @@ gpmc_to_fifo_async.v \
 gpmc_to_fifo_sync.v \
 gpmc_wb.v \
 ram_to_fifo.v \
+new_write.v \
+new_read.v \
 ))
diff --git a/fpga/usrp2/gpmc/fifo_watcher.v b/fpga/usrp2/gpmc/fifo_watcher.v
index b139f5143..3971e3c54 100644
--- a/fpga/usrp2/gpmc/fifo_watcher.v
+++ b/fpga/usrp2/gpmc/fifo_watcher.v
@@ -30,10 +30,11 @@ module fifo_watcher
    reg [15:0] counter;
    wire [4:0] pkt_count;
    assign debug = pkt_count;
+   wire       space;
    
    fifo_short #(.WIDTH(16)) frame_lengths
      (.clk(clk), .reset(reset), .clear(clear),
-      .datain(counter), .src_rdy_i(write), .dst_rdy_o(),
+      .datain(counter), .src_rdy_i(write), .dst_rdy_o(space),
       .dataout(length), .src_rdy_o(have_packet_int), .dst_rdy_i(read),
       .occupied(pkt_count), .space());
 
@@ -53,7 +54,9 @@ module fifo_watcher
        bus_error <= 1;
      else if(read & ~have_packet_int)
        bus_error <= 1;
-
+     else if(write & ~space)
+       bus_error <= 1;
+   
    reg 	      in_packet;
    always @(posedge clk)
      if(reset | clear)
diff --git a/fpga/usrp2/gpmc/gpmc_async.v b/fpga/usrp2/gpmc/gpmc_async.v
index c0bec683a..9972e81b0 100644
--- a/fpga/usrp2/gpmc/gpmc_async.v
+++ b/fpga/usrp2/gpmc/gpmc_async.v
@@ -22,7 +22,7 @@ module gpmc_async
     parameter RXFIFOSIZE = 11,
     parameter BUSDEBUG = 1)
    (// GPMC signals
-    input arst,
+    input arst, input bus_clk,
     input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
     input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
     
@@ -67,27 +67,21 @@ module gpmc_async
    // ////////////////////////////////////////////
    // TX Data Path
 
-   wire [17:0] 	  tx18_data, tx18b_data;
-   wire 	  tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy;
+   wire [17:0] 	  tx18_data;
+   wire 	  tx18_src_rdy, tx18_dst_rdy;
    wire [15:0] 	  tx_fifo_space;
    wire [35:0] 	  tx36_data, tx_data;
    wire 	  tx36_src_rdy, tx36_dst_rdy, tx_src_rdy, tx_dst_rdy;
    
-   gpmc_to_fifo_async gpmc_to_fifo_async
+   new_write new_write
      (.EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE),
-      .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), .clear(clear_tx),
+      .bus_clk(bus_clk), .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), .clear(clear_tx),
       .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy),
-      .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space),
-      .bus_error(bus_error_tx) );
+      .frame_len(tx_frame_len), .fifo_ready(tx_have_space), .bus_error(bus_error_tx) );
    
-   fifo_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
-      .datain(tx18_data), .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space),
-      .dataout(tx18b_data), .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied());
-
    fifo19_to_fifo36 #(.LE(1)) f19_to_f36   // Little endian because ARM is LE
      (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
-      .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy),
+      .f19_datain({1'b0,tx18_data}), .f19_src_rdy_i(tx18_src_rdy), .f19_dst_rdy_o(tx18_dst_rdy),
       .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy));
    
    fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36
@@ -110,31 +104,20 @@ module gpmc_async
       .datain(rx_data), .src_rdy_i(rx_src_rdy), .dst_rdy_o(rx_dst_rdy),
       .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy));
 
+   wire [31:0] 	pkt_count;
+   wire 	throttle = pkt_count == 16;
+   
    fifo36_to_fifo19 #(.LE(1)) f36_to_f19   // Little endian because ARM is LE
      (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
       .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy),
       .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) );
 
-   fifo_cascade #(.WIDTH(18), .SIZE(12)) rx_fifo
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
-      .datain(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space),
-      .dataout(rx18b_data), .src_rdy_o(rx18b_src_rdy), .dst_rdy_i(rx18b_dst_rdy), .occupied());
-
-   fifo_to_gpmc_async fifo_to_gpmc_async
+   new_read new_read
      (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
-      .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy),
+      .data_i(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy),
       .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE),
-      .frame_len(rx_frame_len) );
-
-   wire [31:0] 	pkt_count;
+      .have_packet(rx_have_data), .frame_len(rx_frame_len), .bus_error(bus_error_rx) );
    
-   fifo_watcher fifo_watcher
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
-      .src_rdy1(rx18_src_rdy), .dst_rdy1(rx18_dst_rdy), .sof1(rx18_data[16]), .eof1(rx18_data[17]),
-      .src_rdy2(rx18b_src_rdy), .dst_rdy2(rx18b_dst_rdy), .sof2(rx18b_data[16]), .eof2(rx18b_data[17]),
-      .have_packet(rx_have_data), .length(rx_frame_len), .bus_error(bus_error_rx),
-      .debug(pkt_count));
-
    // ////////////////////////////////////////////
    // Control path on CS6
    
@@ -230,16 +213,13 @@ module gpmc_async
    // FIXME -- make sure packet completes before we shutoff
    // FIXME -- handle overrun and underrun
 
-wire [0:17] dummy18;
-
-assign debug = {8'd0,
-		test_rate,
-		pkt_src_enable, pkt_sink_enable, timedrx_src_rdy_int, timedrx_dst_rdy_int,
-		timedrx_src_rdy, timedrx_dst_rdy,
-		testrx_src_rdy, testrx_dst_rdy,
-		rx_src_rdy, rx_dst_rdy,
-		rx36_src_rdy, rx36_dst_rdy,
-		rx18_src_rdy, rx18_dst_rdy,
-		rx18b_src_rdy, rx18b_dst_rdy};
+   wire [0:17] 	dummy18;
+
+   assign debug = {rx_overrun, tx_underrun, bus_error_tx, bus_error_rx, tx_have_space, rx_have_data, EM_NCS4, EM_NCS6,
+		   6'd0, EM_NOE, EM_NWE,
+		   pkt_src_enable, pkt_sink_enable, timedrx_src_rdy_int, timedrx_dst_rdy_int,
+		   timedrx_src_rdy, timedrx_dst_rdy,
+		   testrx_src_rdy, testrx_dst_rdy,
+		   rx_src_rdy, rx_dst_rdy, rx36_src_rdy, rx36_dst_rdy, rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy};
 
 endmodule // gpmc_async
diff --git a/fpga/usrp2/gpmc/new_read.v b/fpga/usrp2/gpmc/new_read.v
new file mode 100644
index 000000000..ae3db23cf
--- /dev/null
+++ b/fpga/usrp2/gpmc/new_read.v
@@ -0,0 +1,62 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+
+module new_read
+  (input clk, input reset, input clear,
+   input [17:0] data_i, input src_rdy_i, output dst_rdy_o,
+   output reg [15:0] EM_D, input EM_NCS, input EM_NOE,
+   output have_packet, output [15:0] frame_len, output bus_error);
+
+   wire [17:0] 	data_int;
+   wire 	src_rdy_int, dst_rdy_int;
+   
+   fifo_cascade #(.WIDTH(18), .SIZE(12)) rx_fifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), .space(),
+      .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied());
+
+   fifo_watcher fifo_watcher
+     (.clk(clk), .reset(reset), .clear(clear),
+      .src_rdy1(src_rdy_i), .dst_rdy1(dst_rdy_o), .sof1(data_i[16]), .eof1(data_i[17]),
+      .src_rdy2(src_rdy_int), .dst_rdy2(dst_rdy_int), .sof2(data_int[16]), .eof2(data_int[17]),
+      .have_packet(have_packet), .length(frame_len), .bus_error(bus_error),
+      .debug());
+   
+   // Synchronize the async control signals
+   reg [1:0] 	cs_del, oe_del;
+   reg [15:0] 	counter;
+   
+   always @(posedge clk)
+     if(reset)
+       begin
+	  cs_del <= 2'b11;
+	  oe_del <= 2'b11;
+       end
+     else
+       begin
+	  cs_del <= { cs_del[0], EM_NCS };
+	  oe_del <= { oe_del[0], EM_NOE };
+       end
+
+   assign dst_rdy_int = ( ~cs_del[1] & ~oe_del[1] & oe_del[0]);  // change output on trailing edge
+
+   //always @(posedge clk)   // 3 cycle latency ( OE -> OE_del -> FIFO -> output REG )
+   always @*                 // 2 cycle latency ( OE -> OE_del -> FIFO )
+     EM_D <= data_int[15:0];
+   
+endmodule // new_read
diff --git a/fpga/usrp2/gpmc/new_write.v b/fpga/usrp2/gpmc/new_write.v
new file mode 100644
index 000000000..df0ce19db
--- /dev/null
+++ b/fpga/usrp2/gpmc/new_write.v
@@ -0,0 +1,82 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+
+module new_write
+  (input [15:0] EM_D, input [1:0] EM_NBE, input EM_NCS, input EM_NWE,
+
+   input bus_clk,
+   input fifo_clk, input fifo_rst, input clear,
+   output [17:0] data_o, output src_rdy_o, input dst_rdy_i,
+
+   input [15:0] frame_len, output reg fifo_ready,
+   output reg bus_error );
+
+   wire [15:0] fifo_space;
+   reg [15:0]  counter;
+
+   // Synchronize the async control signals
+   reg [1:0] 	cs_del, we_del;
+   reg [15:0] 	data_del[0:1];
+   
+   always @(posedge bus_clk)
+     if(fifo_rst)
+       begin
+	  cs_del <= 2'b11;
+	  we_del <= 2'b11;
+       end
+     else
+       begin
+	  cs_del <= { cs_del[0], EM_NCS };
+	  we_del <= { we_del[0], EM_NWE };
+	  data_del[1] <= data_del[0];
+	  data_del[0] <= EM_D;
+       end
+
+   wire first_write = (counter == 0);
+   wire last_write = ((counter+1) == frame_len);
+
+   wire [17:0] data_int = {last_write,first_write,data_del[1]};
+   wire        src_rdy_int = (~cs_del[1] & ~we_del[1] & we_del[0]); // rising edge
+   wire        dst_rdy_int;
+   
+   always @(posedge bus_clk)
+     if(fifo_rst | clear)
+       counter <= 0;
+     else if(src_rdy_int)
+       if(last_write)
+	 counter <= 0;
+       else
+	 counter <= counter + 1;
+
+   always @(posedge bus_clk)
+     if(fifo_rst | clear)
+       fifo_ready <= 0;
+     else
+       fifo_ready <= /* first_write & */ (fifo_space > 16'd1023);
+
+   always @(posedge bus_clk)
+     if(fifo_rst | clear)
+       bus_error <= 0;
+     else if(src_rdy_int & ~dst_rdy_int)
+       bus_error <= 1;
+
+   fifo_2clock_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo
+     (.wclk(bus_clk), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(fifo_space),
+      .rclk(fifo_clk), .dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), .occupied(), .arst(fifo_rst));
+
+endmodule // new_write