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| author | Josh Blum <josh@joshknows.com> | 2011-03-10 14:57:01 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-03-10 14:57:01 -0800 |
| commit | db2b80617d789484b463ab81a94605adfae39de9 (patch) | |
| tree | 5f1a85be7a10d76b82ba9c300005573790d1a688 /fpga/usrp2/extramfifo/fifo_extram_tb.build | |
| parent | 6d744744d88f8834f91c76742cd190e204f2ae8e (diff) | |
| parent | 912a697adbfcf80cc64e9c0884f6d723e6d8f003 (diff) | |
| download | uhd-db2b80617d789484b463ab81a94605adfae39de9.tar.gz uhd-db2b80617d789484b463ab81a94605adfae39de9.tar.bz2 uhd-db2b80617d789484b463ab81a94605adfae39de9.zip | |
Merge branch 'packet_router_2nd_dsp' into next
Diffstat (limited to 'fpga/usrp2/extramfifo/fifo_extram_tb.build')
| -rwxr-xr-x | fpga/usrp2/extramfifo/fifo_extram_tb.build | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/fpga/usrp2/extramfifo/fifo_extram_tb.build b/fpga/usrp2/extramfifo/fifo_extram_tb.build deleted file mode 100755 index 5607c8691..000000000 --- a/fpga/usrp2/extramfifo/fifo_extram_tb.build +++ /dev/null @@ -1 +0,0 @@ -iverilog -y ../models -y . -y ../control_lib/ -y ../coregen -y ../fifo -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram_tb fifo_extram_tb.v |