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| author | Josh Blum <josh@joshknows.com> | 2010-11-23 15:35:48 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-11-23 15:35:48 -0800 |
| commit | f56c1247cbe7b7e90acee2711b5dda3356b9486a (patch) | |
| tree | 81dadc83537c2c50550cd94e224571e472176c6f /fpga/usrp2/coregen/coregen.cgp | |
| parent | 9f94ef843ceca63bcb83b2d473cbba709c9110b6 (diff) | |
| parent | eb26e8adb4a5718ee3db3bb7f32c0cd31d060af9 (diff) | |
| download | uhd-f56c1247cbe7b7e90acee2711b5dda3356b9486a.tar.gz uhd-f56c1247cbe7b7e90acee2711b5dda3356b9486a.tar.bz2 uhd-f56c1247cbe7b7e90acee2711b5dda3356b9486a.zip | |
Merge branch 'next' of ettus.sourcerepo.com:ettus/uhdpriv into next
Diffstat (limited to 'fpga/usrp2/coregen/coregen.cgp')
| -rw-r--r-- | fpga/usrp2/coregen/coregen.cgp | 24 |
1 files changed, 13 insertions, 11 deletions
diff --git a/fpga/usrp2/coregen/coregen.cgp b/fpga/usrp2/coregen/coregen.cgp index 810d64dac..dd85a7f50 100644 --- a/fpga/usrp2/coregen/coregen.cgp +++ b/fpga/usrp2/coregen/coregen.cgp @@ -1,20 +1,22 @@ -# Date: Thu Sep 3 17:40:48 2009 -SET addpads = False -SET asysymbol = False +# Date: Fri Oct 15 07:50:19 2010 + +SET addpads = false +SET asysymbol = false SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False +SET createndf = false SET designentry = Verilog SET device = xc3s2000 SET devicefamily = spartan3 SET flowvendor = Other -SET formalverification = False -SET foundationsym = False +SET formalverification = false +SET foundationsym = false SET implementationfiletype = Ngc SET package = fg456 -SET removerpms = False -SET simulationfiles = Behavioral +SET removerpms = false +SET simulationfiles = Structural SET speedgrade = -5 -SET verilogsim = True -SET vhdlsim = False -SET workingdirectory = /home/matt/coregen/tmp +SET verilogsim = true +SET vhdlsim = false +SET workingdirectory = /tmp/ +# CRC: 983b9b45 |