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| author | Matt Ettus <matt@ettus.com> | 2010-03-24 16:36:16 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-03-24 16:36:16 -0700 |
| commit | fc32fa87bc579dfcb04a7a404e6785ac0dc86949 (patch) | |
| tree | 0fc6085d23bf4ddfe425e4f04a4eee2a2a2f2b5d | |
| parent | 8bf96b82706d8a61cb4140dca713479a13ff4f55 (diff) | |
| download | uhd-fc32fa87bc579dfcb04a7a404e6785ac0dc86949.tar.gz uhd-fc32fa87bc579dfcb04a7a404e6785ac0dc86949.tar.bz2 uhd-fc32fa87bc579dfcb04a7a404e6785ac0dc86949.zip | |
Xilinx ISE is incorrectly parsing the verilog case statement, this is a workaround
| -rw-r--r-- | usrp2/vrt/vita_rx_control.v | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/usrp2/vrt/vita_rx_control.v b/usrp2/vrt/vita_rx_control.v index 2e96e6d42..669b8299d 100644 --- a/usrp2/vrt/vita_rx_control.v +++ b/usrp2/vrt/vita_rx_control.v @@ -155,7 +155,13 @@ module vita_rx_control ibs_state <= IBS_RUNNING; end end // else: !if(full) - IBS_OVERRUN, IBS_LATECMD, IBS_BROKENCHAIN : + IBS_OVERRUN : + if(sample_fifo_in_rdy) + ibs_state <= IBS_IDLE; + IBS_LATECMD : + if(sample_fifo_in_rdy) + ibs_state <= IBS_IDLE; + IBS_BROKENCHAIN : if(sample_fifo_in_rdy) ibs_state <= IBS_IDLE; endcase // case(ibs_state) |